Patch set updated for coreboot: Fix GM45 regression from "northbridge/intel/peg: Disable unused ports"

[Jean Lucas]

Jean Lucas ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13607

-gerrit

commit f13b3510a8f30c0750949ba5fbbc02b7208b0b91
Author: Jean Lucas 
Date:   Thu Feb 4 19:29:10 2016 -0500

Fix GM45 regression from "northbridge/intel/peg: Disable unused ports"

The `d->link_list' condition in the gm45_init function breaks GM45.
    Remove it to restore detection and initialization.

Change-Id: Ic7e116c887b854fd1bce1758a718d963ee0ee5a3
    Signed-off-by: Jean Lucas 
---
 src/northbridge/intel/gm45/northbridge.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 84df62d..dee6602 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -279,7 +279,7 @@ static void gm45_init(void *const chip_info)
    	for (; fn >= 0; --fn) {
    		const struct device *const d =
    			dev_find_slot(0, PCI_DEVFN(dev, fn));
-			if (d && d->enabled && d->link_list && !scan_bus_unused(d->link_list))
+			if (d && d->enabled && !scan_bus_unused(d->link_list))
    			continue;
    		const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
    		pci_write_config32(d0f0, D0F0_DEVEN,