Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56954 )
Change subject: mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC ID ......................................................................
mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC ID
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None BRANCH=None TEST=Check if there is no functional impact on the board.
Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 4 files changed, 4 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/56954/1
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 4a0c49f..27f3211 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake
- device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e2a84f8..abb8bdc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -79,9 +79,7 @@
chip soc/intel/tigerlake
- device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4e3d2e79..66eb027 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake
- device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7f7e16b..c4bbdda 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake
- device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end
# GPE configuration # Note that GPE events called out in ASL code rely on this