[XS] Change in coreboot[main]: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84177?usp=email )

Change subject: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support
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mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support

Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1.

lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled.

BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607
Signed-off-by: Jian Tong 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84177
Reviewed-by: Kun Liu 
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
---
M src/mainboard/google/brox/variants/lotso/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Karthik Ramasubramanian: Looks good to me, approved
  build bot (Jenkins): Verified
  Kun Liu: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index 0f87889..09e8815 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -357,6 +357,7 @@
    			.clk_src = 3,
    			.clk_req = 3,
    			.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
    		}"
    		chip soc/intel/common/block/pcie/rtd3
    			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"