Change in coreboot[master]: mb/google/guybrush/var/nipperkin: enhance U2 driving strength

[Kevin Chiu (Code Review)]

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60089 )

Change subject: mb/google/guybrush/var/nipperkin: enhance U2 driving strength
......................................................................

mb/google/guybrush/var/nipperkin: enhance U2 driving strength

BUG=b:203049656
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Change-Id: If5a6563e93bfa6beb529a5593fcc9124ce62d77f
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
1 file changed, 133 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/60089/1

diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index 2d3b162..cee3556 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -27,6 +27,139 @@
 end

chip soc/amd/cezanne
+
+	register "usb_phy_custom" = "1"
+	register "usb_phy" = "{
+		/* Left USB C0 Port */
+		.Usb2PhyPort[0] = {
+			.compdstune = 5,
+			.sqrxtune = 3,
+			.txfslstune = 3,
+			.txpreempamptune = 1,
+			.txpreemppulsetune = 0,
+			.txrisetune = 1,
+			.txvreftune = 9,
+			.txhsxvtune = 3,
+			.txrestune = 1,
+		},
+		/* Left USB A0 Port or WWAN */
+		.Usb2PhyPort[1] = {
+			.compdstune = 5,
+			.sqrxtune = 3,
+			.txfslstune = 3,
+			.txpreempamptune = 1,
+			.txpreemppulsetune = 0,
+			.txrisetune = 1,
+			.txvreftune = 9,
+			.txhsxvtune = 3,
+			.txrestune = 1,
+		},
+		/* User facing camera */
+		.Usb2PhyPort[2] = {
+			.compdstune = 1,
+			.sqrxtune = 3,
+			.txfslstune = 3,
+			.txpreempamptune = 2,
+			.txpreemppulsetune = 0,
+			.txrisetune = 2,
+			.txvreftune = 3,
+			.txhsxvtune = 3,
+			.txrestune = 2,
+		},
+		/* World facing camera */
+		.Usb2PhyPort[3] = {
+			.compdstune = 1,
+			.sqrxtune = 3,
+			.txfslstune = 3,
+			.txpreempamptune = 2,
+			.txpreemppulsetune = 0,
+			.txrisetune = 2,
+			.txvreftune = 3,
+			.txhsxvtune = 3,
+			.txrestune = 2,
+		},
+		/* Right USB C1 Port */
+		.Usb2PhyPort[4] = {
+			.compdstune = 6,
+			.sqrxtune = 3,
+			.txfslstune = 3,
+			.txpreempamptune = 1,
+			.txpreemppulsetune = 0,
+			.txrisetune = 1,
+			.txvreftune = 0xe,
+			.txhsxvtune = 3,
+			.txrestune = 1,
+		},
+		/* Right USB A1 Port */
+		.Usb2PhyPort[5] = {
+			.compdstune = 5,
+			.sqrxtune = 3,
+			.txfslstune = 3,
+			.txpreempamptune = 1,
+			.txpreemppulsetune = 0,
+			.txrisetune = 1,
+			.txvreftune = 9,
+			.txhsxvtune = 3,
+			.txrestune = 1,
+		},
+		/* WiFi / Bluetooth */
+		.Usb2PhyPort[6] = {
+			.compdstune = 1,
+			.sqrxtune = 3,
+			.txfslstune = 3,
+			.txpreempamptune = 2,
+			.txpreemppulsetune = 0,
+			.txrisetune = 2,
+			.txvreftune = 3,
+			.txhsxvtune = 3,
+			.txrestune = 2,
+		},
+		/* Smart Card */
+		.Usb2PhyPort[7] = {
+			.compdstune = 1,
+			.sqrxtune = 3,
+			.txfslstune = 3,
+			.txpreempamptune = 2,
+			.txpreemppulsetune = 0,
+			.txrisetune = 2,
+			.txvreftune = 3,
+			.txhsxvtune = 3,
+			.txrestune = 2,
+		},
+		/* Left USB C0 Port */
+		.Usb3PhyPort[0] = {
+			.tx_term_ctrl=2,
+			.rx_term_ctrl=2,
+			.tx_vboost_lvl_en=1,
+			.tx_vboost_lvl=5,
+		},
+		/* Left USB A0 Port or WWAN */
+		.Usb3PhyPort[1] = {
+			.tx_term_ctrl=2,
+			.rx_term_ctrl=2,
+			.tx_vboost_lvl_en=1,
+			.tx_vboost_lvl=5,
+		},
+		/* Right USB C1 Port */
+		.Usb3PhyPort[2] = {
+			.tx_term_ctrl=2,
+			.rx_term_ctrl=2,
+			.tx_vboost_lvl_en=1,
+			.tx_vboost_lvl=5,
+		},
+		/* Right USB A1 Port */
+		.Usb3PhyPort[3] = {
+			.tx_term_ctrl=2,
+			.rx_term_ctrl=2,
+			.tx_vboost_lvl_en=1,
+			.tx_vboost_lvl=5,
+		},
+		.ComboPhyStaticConfig[0] = 0,
+		.ComboPhyStaticConfig[1] = 0,
+		.BatteryChargerEnable = 0,
+		.PhyP3CpmP4Support = 0,
+	}"
+
    device domain 0 on
    	device ref gpp_bridge_2 on
    		# Required so the NVMe gets placed into D3 when entering S0i3.