Change in coreboot[master]: mb/intel/tigerlake_rvp: Add TGL UP3 and UP4 RVP DIMM configuration

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36244 )

Change subject: mb/intel/tigerlake_rvp: Add TGL UP3 and UP4 RVP DIMM configuration
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Patch Set 4:

(3 comments)

https://review.coreboot.org/c/coreboot/+/36244/4/src/mainboard/intel/tigerla... 
File src/mainboard/intel/tigerlake_rvp/board_id.h:

https://review.coreboot.org/c/coreboot/+/36244/4/src/mainboard/intel/tigerla... 
PS4, Line 23: #define TGL_UP3_LP4_SAMSUNG	0x3
            : #define TGL_UP3_LP4_HYNIX	0xB
            : #define TGL_UP3_LP4_MICRON	0x13
            : #define TGL_UP3_DDR4		0xA
            : 
            : /* TGL-Y Board IDs */
            : #define TGL_UP4_LP4_SAMSUNG	0x5
            : #define TGL_UP4_LP4_HYNIX	0xD
            : #define TGL_UP4_LP4_MICRON	0x15
Those are unused in this CL.

https://review.coreboot.org/c/coreboot/+/36244/4/src/mainboard/intel/tigerla... 
File src/mainboard/intel/tigerlake_rvp/board_id.c:

https://review.coreboot.org/c/coreboot/+/36244/4/src/mainboard/intel/tigerla... 
PS4, Line 23: uint32_t
the return type is int.

https://review.coreboot.org/c/coreboot/+/36244/4/src/mainboard/intel/tigerla... 
PS4, Line 34: MAYBE_STATIC_NONZERO
Do you expect stages without .bss? Won't just static work?