[S] Change in coreboot[master]: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock

[Werner Zeh (Code Review)]

Attention is currently required from: Lean Sheng Tan.

Hello build bot (Jenkins), Angel Pons, Lean Sheng Tan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/68669

to look at the new patch set (#2).

Change subject: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
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soc/intel/elkhartlake: Fix incorrect divider for MDIO clock

After some measurements it turned out that Elkhart Lake uses a higher
CSR clock internally from which the MDIO clock is derived. In order to
stay compliant with the specification, the MDIO clock needs to be lower
than 2.5 MHz. Therefore, the divider needs to be 102 and not 62.
This patch changes the define to match the new divider value and uses
this new define at the appropriate place.

Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz.

Change-Id: Idf498c3547530dfa395f54488ef244e787062e34
Signed-off-by: Werner Zeh 
---
M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
M src/soc/intel/elkhartlake/tsn_gbe.c
2 files changed, 22 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/68669/2