Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34869 )
Change subject: intel/smm/gen1: Rename header file ......................................................................
intel/smm/gen1: Rename header file
The interfaces are getting unified, make this a transitional indirect include for a moment.
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c A src/include/cpu/intel/smm_reloc.h M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/common/smi.c 19 files changed, 37 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/34869/1
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e47712c..ce2b9e5 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -24,7 +24,7 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h> #include "chip.h"
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 73c9a47..312660b 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -19,7 +19,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h> #include <device/device.h>
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 2f10945..b588095 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/name.h> #include "model_2065x.h" #include "chip.h" -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h>
/* diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d3aa52c..4dbe4d9 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -32,7 +32,7 @@ #include <pc80/mc146818rtc.h> #include "model_206ax.h" #include "chip.h" -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h>
/* diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h new file mode 100644 index 0000000..1dbdcda --- /dev/null +++ b/src/include/cpu/intel/smm_reloc.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __INTEL_SMM_RELOC_H__ +#define __INTEL_SMM_RELOC_H__ + +#include <cpu/intel/smm/gen1/smi.h> + +#endif diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 71037ae..ceb6476 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -27,7 +27,7 @@ #include <cbmem.h> #include <program_loading.h> #include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include "gm45.h"
/* diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 1c01d30..384d98a 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -23,7 +23,7 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
#include "chip.h" #include "gm45.h" diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 6092c25..f2518f4 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -24,7 +24,7 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <stdint.h> #include <stage_cache.h>
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index cd16958..dd4e8ac 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -23,7 +23,7 @@ #include <stdlib.h> #include <cpu/cpu.h> #include <arch/acpi.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include "i945.h"
static int get_pcie_bar(u32 *base) diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index 031240c..d592aea 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -24,7 +24,7 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include "nehalem.h"
static uintptr_t smm_region_start(void) diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index b6741a8..4ab89ad 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -29,7 +29,7 @@ #include <cpu/cpu.h> #include "chip.h" #include "nehalem.h" -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
static int bridge_revision_id = -1;
diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 5bfc934..8c19852 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include "nehalem.h"
-#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
void northbridge_write_smram(u8 smram) { diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 2e02889..8be63ef 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -25,7 +25,7 @@ #include <northbridge/intel/pineview/pineview.h> #include <cpu/x86/mtrr.h> #include <cpu/intel/romstage.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <stdint.h> #include <stage_cache.h>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 5a4eec6..34cb583 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -25,7 +25,7 @@ #include <boot/tables.h> #include <arch/acpi.h> #include <northbridge/intel/pineview/pineview.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
/* Reserve everything between A segment and 1MB: * diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 83a67ab..9e2e333 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -20,7 +20,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <stage_cache.h> diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 32b7a4c..58f4a68 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -28,7 +28,7 @@ #include <cpu/cpu.h> #include "chip.h" #include "sandybridge.h" -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
static int bridge_revision_id = -1;
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index a61d64e..9480fc0 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -28,7 +28,7 @@ #include <cpu/x86/mtrr.h> #include <northbridge/intel/x4x/x4x.h> #include <program_loading.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <stage_cache.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index f541e3a..ee70527 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -27,7 +27,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
static const int legacy_hole_base_k = 0xa0000 / 1024;
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 398c680..dafb732 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h>
Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34869
to look at the new patch set (#2).
Change subject: intel/smm/gen1: Rename header file ......................................................................
intel/smm/gen1: Rename header file
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c R src/include/cpu/intel/smm_reloc.h M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/common/smi.c 19 files changed, 33 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/34869/2
Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34869
to look at the new patch set (#3).
Change subject: intel/smm/gen1: Rename header file ......................................................................
intel/smm/gen1: Rename header file
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/gen1/smmrelocate.c R src/include/cpu/intel/smm_reloc.h M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/common/smi.c 20 files changed, 34 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/34869/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34869 )
Change subject: intel/smm/gen1: Rename header file ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34869 )
Change subject: intel/smm/gen1: Rename header file ......................................................................
Patch Set 4:
For the record; we may opt to make this simply <cpu/intel/smm.h> at a later date. Or we may see that what is eventually left i the could go to <cpu/x86/smm.h> instead.
It was a nighmare rebase with these header-files, my own fault, reorder the changeset. I am opting for early merge here and willing to address things later on.
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34869 )
Change subject: intel/smm/gen1: Rename header file ......................................................................
intel/smm/gen1: Rename header file
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34869 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/gen1/smmrelocate.c R src/include/cpu/intel/smm_reloc.h M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/common/smi.c 20 files changed, 34 insertions(+), 28 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e47712c..ce2b9e5 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -24,7 +24,7 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h> #include "chip.h"
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 73c9a47..312660b 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -19,7 +19,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h> #include <device/device.h>
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 2f10945..b588095 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/name.h> #include "model_2065x.h" #include "chip.h" -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h>
/* diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d3aa52c..4dbe4d9 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -32,7 +32,7 @@ #include <pc80/mc146818rtc.h> #include "model_206ax.h" #include "chip.h" -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h>
/* diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index f196706..8401611 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -28,9 +28,9 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <smp/node.h> -#include "smi.h"
#define SMRR_SUPPORTED (1 << 11)
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/include/cpu/intel/smm_reloc.h similarity index 75% rename from src/cpu/intel/smm/gen1/smi.h rename to src/include/cpu/intel/smm_reloc.h index 6623bcc..80094e7 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -11,7 +11,10 @@ * GNU General Public License for more details. */
-#include <device/device.h> +#ifndef __INTEL_SMM_RELOC_H__ +#define __INTEL_SMM_RELOC_H__ + +#include <types.h>
/* These helpers are for performing SMM relocation. */ void southbridge_smm_init(void); @@ -19,14 +22,17 @@ u32 northbridge_get_tseg_size(void); void northbridge_write_smram(u8 smram);
-bool cpu_has_alternative_smrr(void); +void smm_lock(void); +void smm_relocate(void);
/* parallel MP helper functions */ -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); void southbridge_smm_clear_state(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_relocate(void); -void smm_lock(void); + +/* To be removed. */ +void smm_initialize(void); +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); + +bool cpu_has_alternative_smrr(void); + +#endif diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 71037ae..ceb6476 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -27,7 +27,7 @@ #include <cbmem.h> #include <program_loading.h> #include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include "gm45.h"
/* diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 1c01d30..384d98a 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -23,7 +23,7 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
#include "chip.h" #include "gm45.h" diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 6092c25..f2518f4 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -24,7 +24,7 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <stdint.h> #include <stage_cache.h>
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index cd16958..dd4e8ac 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -23,7 +23,7 @@ #include <stdlib.h> #include <cpu/cpu.h> #include <arch/acpi.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include "i945.h"
static int get_pcie_bar(u32 *base) diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index 031240c..d592aea 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -24,7 +24,7 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include "nehalem.h"
static uintptr_t smm_region_start(void) diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index b6741a8..4ab89ad 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -29,7 +29,7 @@ #include <cpu/cpu.h> #include "chip.h" #include "nehalem.h" -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
static int bridge_revision_id = -1;
diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 5bfc934..8c19852 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include "nehalem.h"
-#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
void northbridge_write_smram(u8 smram) { diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 2e02889..8be63ef 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -25,7 +25,7 @@ #include <northbridge/intel/pineview/pineview.h> #include <cpu/x86/mtrr.h> #include <cpu/intel/romstage.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <stdint.h> #include <stage_cache.h>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 5a4eec6..34cb583 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -25,7 +25,7 @@ #include <boot/tables.h> #include <arch/acpi.h> #include <northbridge/intel/pineview/pineview.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
/* Reserve everything between A segment and 1MB: * diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 83a67ab..9e2e333 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -20,7 +20,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <stage_cache.h> diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 32b7a4c..58f4a68 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -28,7 +28,7 @@ #include <cpu/cpu.h> #include "chip.h" #include "sandybridge.h" -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
static int bridge_revision_id = -1;
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index a61d64e..9480fc0 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -28,7 +28,7 @@ #include <cpu/x86/mtrr.h> #include <northbridge/intel/x4x/x4x.h> #include <program_loading.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <stage_cache.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index f541e3a..ee70527 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -27,7 +27,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h>
static const int legacy_hole_base_k = 0xa0000 / 1024;
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 398c680..dafb732 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/smm_reloc.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h>
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