[S] Change in coreboot[master]: lib/ramtest.c: Update ram failure post code

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69202 )

Change subject: lib/ramtest.c: Update ram failure post code
......................................................................

lib/ramtest.c: Update ram failure post code

coreboot already has a ram failure post code defined, but the ram test
functions weren't using it, and were using 0xea instead.
This changes those failures to display 0xe3, the value defined in
post_codes.h by POST_RAM_FAILURE.

Signed-off-by: Martin Roth 
Change-Id: I21ef196e48ff37ffe320b575d6de66b43997e7eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69202
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Matt DeVillier 
---
M src/lib/ramtest.c
1 file changed, 21 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index d6f958f..7ac141a 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -110,7 +110,7 @@
    	}
    }
    if (failures) {
-		post_code(0xea);
+		post_code(POST_RAM_FAILURE);
    	printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
    	return 1;
    }
@@ -200,7 +200,7 @@

write_phys(dst, backup);
    if (fail) {
-		post_code(0xea);
+		post_code(POST_RAM_FAILURE);
    	die("RAM INIT FAILURE!\n");
    }
    phys_memory_barrier();