Change in coreboot[master]: amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35654 )

Change subject: amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE
......................................................................

amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE

Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654
Reviewed-by: Furquan Shaikh 
Reviewed-by: Aaron Durbin 
Tested-by: build bot (Jenkins) 
---
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/quadcore/quadcore_id.c
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdfam10/amdfam10_util.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/southbridge/amd/sr5650/cmn.h
6 files changed, 25 insertions(+), 27 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
index 5b97232..3946b67 100644
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
@@ -65,7 +65,7 @@
    if (is_fam15h()) {
    	enable_cc6 = 0;

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
    	if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
    		enable_cc6 = 1;
 #else
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index 2c4d60d..7ec1bdb 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -42,7 +42,7 @@
    uint32_t family;
    uint32_t model;

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
    f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
 #else
    f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
@@ -109,7 +109,7 @@
    	uint32_t f5x84;
    	uint8_t core_count;

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
    	f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84);
 #else
    	f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84);
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 96938b2..ad8d013 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1017,11 +1017,9 @@

struct acpi_rsdp;

-#ifndef __SIMPLE_DEVICE__
 unsigned long northbridge_write_acpi_tables(struct device *device,
    				    unsigned long start,
    				    struct acpi_rsdp *rsdp);
 void northbridge_acpi_write_vars(struct device *device);
-#endif

#endif /* AMDFAM10_H */
diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
index 3e8c2fb..23e9232 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -21,7 +21,7 @@
 #include "raminit.h"
 #include <northbridge/amd/amdmct/amddefs.h>

-#ifndef __SIMPLE_DEVICE__
+#if !ENV_PCI_SIMPLE_DEVICE
 u32 Get_NB32(u32 dev, u32 reg)
 {
    return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 1fdbc16..52032e9 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -69,7 +69,7 @@
    return s3nv_region.region.offset;
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static uint32_t read_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct,
    			  uint32_t reg)
 #else
@@ -79,7 +79,7 @@
 {
    if (is_fam15h()) {
    	uint32_t dword;
-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
    	pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
    	struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
@@ -98,7 +98,7 @@
    return pci_read_config32(dev, reg);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static void write_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct,
    		       uint32_t reg, uint32_t value)
 #else
@@ -108,7 +108,7 @@
 {
    if (is_fam15h()) {
    	uint32_t dword;
-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
    	pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
    	struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
@@ -127,7 +127,7 @@
    pci_write_config32(dev, reg, value);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static uint32_t read_amd_dct_index_register(pci_devfn_t dev,
    				uint32_t index_ctl_reg, uint32_t index)
 #else
@@ -147,7 +147,7 @@
    return dword;
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static uint32_t read_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node,
    		uint8_t dct, uint32_t index_ctl_reg, uint32_t index)
 #else
@@ -158,7 +158,7 @@
 {
    if (is_fam15h()) {
    	uint32_t dword;
-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
    	pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
    	struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
index d70e7a9..9588105 100644
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -34,7 +34,7 @@
 #define AB_INDX   0xCD8
 #define AB_DATA   (AB_INDX+4)

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
 #else
 static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
@@ -44,7 +44,7 @@
    return pci_read_config32(dev, index_reg + 0x4);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index,
    			  u32 data)
 #else
@@ -56,7 +56,7 @@
    pci_write_config32(dev, index_reg + 0x4, data);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
 #else
 static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)
@@ -65,7 +65,7 @@
    return nb_read_index((nb_dev), NBMISC_INDEX, (index));
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
 #else
 static inline void nbmisc_write_index(struct device *nb_dev, u32 index,
@@ -75,7 +75,7 @@
    nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
    				  u32 mask, u32 val)
 #else
@@ -92,7 +92,7 @@
    }
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
 #else
 static inline u32 htiu_read_index(struct device *nb_dev, u32 index)
@@ -101,7 +101,7 @@
    return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
 #else
 static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
@@ -110,7 +110,7 @@
    nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
 #else
 static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)
@@ -119,7 +119,7 @@
    return nb_read_index((nb_dev), NBMC_INDEX, (index));
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
 #else
 static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
@@ -128,7 +128,7 @@
    nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
    				u32 mask, u32 val)
 #else
@@ -145,7 +145,7 @@
    }
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
    				 u32 mask, u32 val)
 #else
@@ -162,7 +162,7 @@
    }
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos,
    				   u8 mask, u8 val)
 #else
@@ -179,7 +179,7 @@
    }
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
    				u32 mask, u32 val)
 #else
@@ -196,7 +196,7 @@
    }
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask,
    				u32 val)
 #else