[M] Change in coreboot[main]: skl mainboards/dt: Move serirq setting into LPC device scope
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83188?usp=email )
Change subject: skl mainboards/dt: Move serirq setting into LPC device scope ......................................................................
skl mainboards/dt: Move serirq setting into LPC device scope
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb 11 files changed, 25 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/83188/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1f2fa40..3ffc00f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -39,8 +39,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s
- register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enable Root Ports 3, 4 and 9 register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" @@ -116,6 +114,8 @@ device ref pcie_rp4 on end device ref pcie_rp9 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641"
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index c41a26f..763a380 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -18,9 +18,6 @@ register "lpc_iod" = "0x0070" register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66"
- # LPC serial IRQ - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # "Intel SpeedStep Technology" register "eist_enable" = "1"
@@ -214,6 +211,8 @@ device ref uart0 on end device ref emmc on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # CPLD host command ranges are in 0x280-0x2BF # EC PNP registers are at 0x6e and 0x6f register "gen1_dec" = "0x003c0281" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 49edccb..8a3161a 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -4,8 +4,6 @@ register "DspEnable" = "0" register "ScsEmmcHs400Enabled" = "0"
- register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enable PCIE slot register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" @@ -119,5 +117,8 @@ device ref sdxc off end device ref hda on end device ref gbe on end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 5516fee..010312c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -7,8 +7,6 @@ # FSP Configuration register "ScsEmmcHs400Enabled" = "0"
- register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | @@ -173,6 +171,8 @@ device ref emmc off end device ref sdxc off end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + #chip drivers/pc80/tpm # device pnp 0c31.0 on end #end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 73df651..2f5058d 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -32,8 +32,6 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03"
- register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -217,6 +215,9 @@ device ref gspi1 on end device ref hda on end device ref smbus on end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + end device ref fast_spi on end device ref gbe on end end diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f173e1e..a171517 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -9,8 +9,6 @@
register "eist_enable" = "1"
- register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Set the Thermal Control Circuit (TCC) activation value to 95C # even though FSP integration guide says to set it to 100C for SKL-U # (offset at 0), because when the TCC activates at 100C, the CPU @@ -169,6 +167,8 @@ device ref pcie_rp11 on end device ref pcie_rp12 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 5565064..228676b 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -17,9 +17,6 @@ # Disable DPTF register "dptf_enable" = "0"
- # Enable SERIRQ continuous - register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "tcc_offset" = "5" # TCC of 95C
# FSP Configuration @@ -198,6 +195,8 @@ "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x007c0a01" register "gen3_dec" = "0x000c03e1" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 7892c7e..ca18f7a 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -47,9 +47,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s
- # EC/KBC requires continuous mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -153,6 +150,9 @@ device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" chip drivers/pc80/tpm diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 438d323..b8ebb1b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -28,8 +28,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s
- register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -172,6 +170,8 @@ device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 29759fd..fbf896c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -4,9 +4,6 @@ register "SkipExtGfxScan" = "1"
- # LPC - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch register "s0ix_enable" = true register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" @@ -33,6 +30,8 @@ }" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip superio/common device pnp 2e.0 on end end diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 38578e0..e4658a7 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -18,9 +18,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART }"
- # Serial IRQ - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Power register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -172,6 +169,8 @@ register "PcieRpLtrEnable[8]" = "1" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" register "gen3_dec" = "0x00040069"
-
Felix Singer (Code Review)