Change in coreboot[master]: nb/intel/nehalem: Add some debug output

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36037 )

Change subject: nb/intel/nehalem: Add some debug output
......................................................................

nb/intel/nehalem: Add some debug output

Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/nehalem/raminit.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36037/1

diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 75be572..4618911 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -3730,6 +3730,9 @@
    int cbmem_wasnot_inited;

x2ca8 = MCHBAR8(0x2ca8);
+
+	printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8);
+
    deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN);

memset(&info, 0x5a, sizeof(info));
@@ -4241,6 +4244,8 @@
    if (x2ca8 == 0) {
    	MCHBAR8_AND(0x2ca8, ~3);
    	MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4;	// "+" or  "|"?
+		/* This issues a CPU reset without resetting the platform */
+		printk(BIOS_DEBUG, "Issuing a CPU reset\n");
    	MCHBAR32_OR(0x1af0, 0x10);
    	halt();
    }

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36037 )

Change subject: nb/intel/nehalem: Add some debug output
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36037 )

Change subject: nb/intel/nehalem: Add some debug output
......................................................................

nb/intel/nehalem: Add some debug output

Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36037
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/northbridge/intel/nehalem/raminit.c
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 75be572..4618911 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -3730,6 +3730,9 @@
    int cbmem_wasnot_inited;

x2ca8 = MCHBAR8(0x2ca8);
+
+	printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8);
+
    deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN);

memset(&info, 0x5a, sizeof(info));
@@ -4241,6 +4244,8 @@
    if (x2ca8 == 0) {
    	MCHBAR8_AND(0x2ca8, ~3);
    	MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4;	// "+" or  "|"?
+		/* This issues a CPU reset without resetting the platform */
+		printk(BIOS_DEBUG, "Issuing a CPU reset\n");
    	MCHBAR32_OR(0x1af0, 0x10);
    	halt();
    }