New patch to review for coreboot: af6c2d0 x86: add SMM save state for 0x0100 revision

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4890

-gerrit

commit af6c2d0b6a024cc92027da403cfa8c1bf08c0eec
Author: Aaron Durbin 
Date:   Mon Oct 21 22:21:12 2013 -0500

x86: add SMM save state for 0x0100 revision

The Bay Trail SMM save state revision is 0x0100.
    Add support for this save state area using the
    type named em64t100_smm_state_save_area_t.

BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Built and booted using this structure with forthcoming CLs.

Change-Id: Iddd9498ab9fffcd865dae062526bda2ffcdccbce
    Signed-off-by: Aaron Durbin 
    Reviewed-on: https://chromium-review.googlesource.com/173981
---
 src/include/cpu/x86/smm.h | 86 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index feb50ec..bda1413 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -208,6 +208,92 @@ typedef struct {
 } __attribute__((packed)) em64t_smm_state_save_area_t;

+/* Intel Revision 30100 SMM State-Save Area
+ * The following processor architectures use this:
+ * - Bay Trail
+ */
+#define SMM_EM64T100_ARCH_OFFSET 0x7c00
+#define SMM_EM64T100_SAVE_STATE_OFFSET \
+	SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET)
+typedef struct {
+	u8	reserved0[256];
+	u8	reserved1[208];
+
+	u32	gdtr_upper_base;
+	u32	ldtr_upper_base;
+	u32	idtr_upper_base;
+
+	u8	reserved2[4];
+
+	u64	io_rdi;
+	u64	io_rip;
+	u64	io_rcx;
+	u64	io_rsi;
+
+	u8	reserved3[64];
+	u32	cr4;
+
+	u8	reserved4[72];
+
+	u32	gdtr_base;
+	u8	reserved5[4];
+	u32	idtr_base;
+	u8	reserved6[4];
+	u32	ldtr_base;
+
+	u8	reserved7[88];
+
+	u32	smbase;
+	u32	smm_revision;
+
+	u16	io_restart;
+	u16	autohalt_restart;
+
+	u8	reserved8[24];
+
+	u64	r15;
+	u64	r14;
+	u64	r13;
+	u64	r12;
+	u64	r11;
+	u64	r10;
+	u64	r9;
+	u64	r8;
+
+	u64	rax;
+	u64	rcx;
+	u64	rdx;
+	u64	rbx;
+
+	u64	rsp;
+	u64	rbp;
+	u64	rsi;
+	u64	rdi;
+
+
+	u64	io_mem_addr;
+	u32	io_misc_info;
+
+	u32	es_sel;
+	u32	cs_sel;
+	u32	ss_sel;
+	u32	ds_sel;
+	u32	fs_sel;
+	u32	gs_sel;
+
+	u32	ldtr_sel;
+	u32	tr_sel;
+
+	u64	dr7;
+	u64	dr6;
+	u64	rip;
+	u64	efer;
+	u64	rflags;
+
+	u64	cr3;
+	u64	cr0;
+} __attribute__((packed)) em64t100_smm_state_save_area_t;
+
 /* Intel Revision 30101 SMM State-Save Area
  * The following processor architectures use this:
  * - SandyBridge