Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56859 )
Change subject: soc/intel/alderlake: Use romstage common stage file ......................................................................
soc/intel/alderlake: Use romstage common stage file
This patch will enable alderlake romstage code to utilize common code implementation.
Signed-off-by: Bernardo Perez Priego bernardo.perez.priego@intel.com Change-Id: I03ea050abe6f78d59665f82641a13e7d8b2d6ddc --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/romstage/romstage.c 3 files changed, 15 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/56859/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4cc4157..a33f85c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -45,6 +45,8 @@ select PMC_EPOC select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_ROMSTAGE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index f9b3d60..58de9d4 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include <cpu/x86/msr.h> #include <device/device.h> #include <fsp/util.h> +#include <intelbasecode/romstage.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/pcie_rp.h> @@ -311,9 +312,10 @@ } }
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_alderlake_config *config) +void romstage_soc_mem_init_params(FSPM_UPD *mupd, uint32_t version) { + const struct soc_intel_alderlake_config *config; + FSP_M_CONFIG *m_cfg; const void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) = { fill_fspm_igd_params, @@ -333,19 +335,16 @@ fill_fspm_trace_params, };
+ config = config_of_soc(); + m_cfg = &mupd->FspmConfig; + for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) fill_fspm_params[i](m_cfg, config); }
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +void romstage_mb_mem_init_params(FSPM_UPD *mupd) { - const struct soc_intel_alderlake_config *config; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - config = config_of_soc(); - - soc_memory_init_params(m_cfg, config); - mainboard_memory_init_params(m_cfg); + mainboard_memory_init_params(&mupd->FspmConfig); }
__weak void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index eab734f..53fa00f 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -2,15 +2,10 @@
#include <arch/romstage.h> #include <console/console.h> -#include <intelblocks/cfg.h> +#include <intelbasecode/romstage.h> #include <intelblocks/cse.h> #include <intelblocks/meminfo.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/smbus.h> -#include <soc/iomap.h> -#include <soc/pm.h> #include <soc/romstage.h> -#include <string.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -18,22 +13,11 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ }
-void mainboard_romstage_entry(void) +void romstage_soc_post_mem_init(void) { - bool s3wake; - struct chipset_power_state *ps = pmc_get_power_state(); + romstage_cmn_soc_post_mem_init();
- /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - /* Program SMBus base address and enable it */ - smbus_common_init(); - /* Initialize HECI interface */ - heci_init(HECI1_BASE_ADDRESS); - - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); - pmc_set_disb(); - if (!s3wake) { + if (!romstage_is_s3wake()) { const uint8_t guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; /* * cse_fw_sync() must be called after DRAM initialization as