mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocation for bl31 ......................................................................
sc7180: Adjust memory allocation for bl31
Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39362/1
diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 7323119..930d4a8 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -62,7 +62,7 @@ /* Various hardware/software subsystems make use of this area */ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x300000, 0x1000) - BL31(0x80C00000, 0x1A800000) + BL31(0x80C00000, 2M) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) }
Hello build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39362
to look at the new patch set (#2).
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
sc7180: Adjust memory allocations per upstream comments
Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39362/2
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... PS3, Line 65: 0x300000 Saurabh said that we don't need the TZ_STAT region for coreboot builds, so can we reduce this to 2MB now? (Also would be more readable to write this as 2M and dram_aop as 256K.)
Can move BL31 down to 0x80B00000 then to avoid leaving a hole.
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... PS3, Line 66: 2M Comments on the bug said 1MB, any reason why it needs to be 2 now? (Remember we can always update this if it grows later, there's no need to leave room for expansion here.
mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... PS3, Line 65: 0x300000
Saurabh said that we don't need the TZ_STAT region for coreboot builds, so can we reduce this to 2MB […]
Will confirm that ATF team is good to move bl31 down to 0x80B00000.
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... PS3, Line 66: 2M
Comments on the bug said 1MB, any reason why it needs to be 2 now? (Remember we can always update th […]
Version of bl31 Google has requires 2MB. When new version is available that reduces hard-coded constant to 1M, this will be updated to only use 1M. We didn't want to break your builds.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
Patch Set 6:
*ping*
Any update on the two open comment issues?
Hello Ravi kumar, build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39362
to look at the new patch set (#7).
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
sc7180: Adjust memory allocations per upstream comments
Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39362/7
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
Patch Set 8: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... PS3, Line 65: 0x300000
Will confirm that ATF team is good to move bl31 down to 0x80B00000.
Done
https://review.coreboot.org/c/coreboot/+/39362/3/src/soc/qualcomm/sc7180/inc... PS3, Line 66: 2M
Version of bl31 Google has requires 2MB. […]
Done
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39362/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39362/8//COMMIT_MSG@8 PS8, Line 8: Please add a commit message body and a Signed-off-by line. The linter won't let me merge it otherwise.
Ravi kumar has uploaded a new patch set (#10) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
sc7180: Adjust memory allocations per upstream comments
Updated memory allocations
Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39362/10
mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39362/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39362/8//COMMIT_MSG@8 PS8, Line 8:
Please add a commit message body and a Signed-off-by line. […]
Done
Hello Ravi kumar, build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39362
to look at the new patch set (#11).
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
sc7180: Adjust memory allocations per upstream comments
Update memory regions, etc.
Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39362/11
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
Patch Set 12: Code-Review+2
Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39362 )
Change subject: sc7180: Adjust memory allocations per upstream comments ......................................................................
sc7180: Adjust memory allocations per upstream comments
Update memory regions, etc.
Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 Signed-off-by: T Michael Turney mturney@codeaurora.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/39362 Reviewed-by: Julius Werner jwerner@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index fc796c1..2a0cd8a 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -27,6 +27,7 @@ SSRAM_END(0x146AE000)
BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) BOOTBLOCK(0x14815000, 40K) PRERAM_CBFS_CACHE(0x1481F000, 70K) PRERAM_CBMEM_CONSOLE(0x14830800, 32K) @@ -48,8 +49,8 @@ DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) - REGION(dram_soc, 0x80900000, 0x300000, 0x1000) - BL31(0x80C00000, 0x1A800000) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 1M) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) }
-
Julius Werner (Code Review) -
mturney mturney (Code Review)
-
Ravi kumar (Code Review)