[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels

[Subrata Banik (Code Review)]

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Eric Lai, Jamie Chen, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Tim Crawford.

Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email )

Change subject: soc/intel/alderlake: Add function to force disable memory channels
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Patch Set 6:

(1 comment)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/85529/comment/fba5299a_ae364394?usp... :
PS1, Line 252: 	if (ch_disable_mask == 0) {
> I have verified that we can disable Mc0Ch0+Mc0Ch1 channels while keeping Mc0Ch2+Mc0Ch3 channels enabled. The same check is present in current patch.
> All other combinations (except above) where Mc0Ch0 is disabled, cannot boot.

I need help from Intel to confirm if disabling  Mc0Ch0+Mc0Ch1 and enabling Mc0Ch2+Mc0Ch3 channels are a valid combination or not ?