Change in coreboot[master]: soc/intel/jsl: Add CdClock config

[Simon Yang (Code Review)]

Attention is currently required from: Jamie Chen, Paul Menzel, Kane Chen, Patrick Rudolph.
Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jsl: Add CdClock config
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Patch Set 9:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60009/comment/eeed33a9_61baf022 
PS7, Line 9: Jasperlake
> Jasper Lake.

Done

https://review.coreboot.org/c/coreboot/+/60009/comment/591c4da7_df206661 
PS7, Line 10:
> Why set it to 0xff?

0xff is the default value of CdClock inside of FSP.