Change in coreboot[master]: soc/inte/alderlake: [TEST]Enable hotplug and configure free clock for...

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Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sugnan Prabhu S, Subrata Banik, Kane Chen, Patrick Rudolph.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52244 )

Change subject: soc/inte/alderlake: [TEST]Enable hotplug and configure free clock for PCIe RPs
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Patch Set 5: Verified+1

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144515):
https://review.coreboot.org/c/coreboot/+/52244/comment/5f0cdcd0_9a6087c6 
PS5, Line 69: 	for (i = 0; i < cfg_count; i++) {
braces {} are not necessary for single statement blocks