Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Kane Chen, Patrick Rudolph.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 23: Verified-1

(3 comments)

File src/soc/intel/jasperlake/fsp_params.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136344):
https://review.coreboot.org/c/coreboot/+/60009/comment/613c75e4_507d7c39 
PS23, Line 212: 	/* 
trailing whitespace

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136344):
https://review.coreboot.org/c/coreboot/+/60009/comment/b673c653_400ad093 
PS23, Line 213: 	 * We intentionally want the default to be maximum value to align with FSP, so we reserve
line over 96 characters

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136344):
https://review.coreboot.org/c/coreboot/+/60009/comment/bc573b65_771267e7 
PS23, Line 215: 	 * 
trailing whitespace