Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47366 )
Change subject: src: Update some incorrect config options in comments ......................................................................
src: Update some incorrect config options in comments
This is a trivial patch to fix some comments that were generating notes in the kconfig lint test.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I26a95f17e82910f50c62215be5c29780fe98e29a --- M src/drivers/i2c/designware/dw_i2c.h M src/ec/google/chromeec/ec_commands.h M src/include/rules.h M src/lib/romstage_handoff.c M src/soc/intel/braswell/memmap.c 5 files changed, 10 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/47366/1
diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index 45f305e..e20a5d1 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -17,7 +17,7 @@
/* * Timing values are in units of clock period, with the clock speed - * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_I2C_CLOCK_MHZ + * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ * Automatic configuration is done based on requested speed, but the * values may need tuned depending on the board and the number of * devices present on the bus. diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 241ec39..fb83d60 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -1388,7 +1388,7 @@ */ EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, /* - * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. + * Early Firmware Selection ver.2. Enabled by VBOOT_EFS2 config option. * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should * be sent to RO to be precise. */ diff --git a/src/include/rules.h b/src/include/rules.h index d30b2b8..6ebb37e 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -63,10 +63,11 @@
/* * NOTE: "verstage" code may either run as a separate stage or linked into the - * bootblock/romstage, depending on the setting of CONFIG_SEPARATE_VERSTAGE. The - * ENV_SEPARATE_VERSTAGE macro will only return true for "verstage" code when - * CONFIG_SEPARATE_VERSTAGE=y, otherwise that code will have ENV_BOOTBLOCK or - * ENV_ROMSTAGE set (depending on the CONFIG_VBOOT_STARTS_IN_... options). + * bootblock/romstage, depending on the setting of the VBOOT_SEPARATE_VERSTAGE + * kconfig option. The ENV_SEPARATE_VERSTAGE macro will only return true for + * "verstage" code when CONFIG(VBOOT_SEPARATE_VERSTAGE) is true, otherwise that + * code will have ENV_BOOTBLOCK or ENV_ROMSTAGE set (depending on the + * "VBOOT_STARTS_IN_"... kconfig options). */ #elif defined(__VERSTAGE__) #define ENV_DECOMPRESSOR 0 diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index b54619d..0a7a822 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -8,7 +8,7 @@
struct romstage_handoff { /* Indicate if the current boot is an S3 resume. If - * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is + * CONFIG_RELOCATABLE_RAMSTAGE is enabled the chipset code is * responsible for initializing this variable. Otherwise, ramstage * will be re-loaded from cbfs (which can be slower since it lives * in flash). */ diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 6cfce43..4a791ef 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -27,11 +27,11 @@ /* * +-------------------------+ Top of RAM (aligned) * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE + * | code and data | Length: CONFIG_SMM_TSEG_SIZE * | (TSEG) | * +-------------------------+ SMM base (aligned) * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | Chipset Reserved Memory | Length: Multiple of CONFIG_SMM_TSEG_SIZE * | | * +-------------------------+ top_of_ram (aligned) * | |
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47366 )
Change subject: src: Update some incorrect config options in comments ......................................................................
Patch Set 1: Code-Review+2
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47366 )
Change subject: src: Update some incorrect config options in comments ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47366 )
Change subject: src: Update some incorrect config options in comments ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47366 )
Change subject: src: Update some incorrect config options in comments ......................................................................
src: Update some incorrect config options in comments
This is a trivial patch to fix some comments that were generating notes in the kconfig lint test.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I26a95f17e82910f50c62215be5c29780fe98e29a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47366 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Christian Walter christian.walter@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/drivers/i2c/designware/dw_i2c.h M src/ec/google/chromeec/ec_commands.h M src/include/rules.h M src/lib/romstage_handoff.c M src/soc/intel/braswell/memmap.c 5 files changed, 10 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved Christian Walter: Looks good to me, approved
diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index 45f305e..e20a5d1 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -17,7 +17,7 @@
/* * Timing values are in units of clock period, with the clock speed - * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_I2C_CLOCK_MHZ + * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ * Automatic configuration is done based on requested speed, but the * values may need tuned depending on the board and the number of * devices present on the bus. diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 241ec39..fb83d60 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -1388,7 +1388,7 @@ */ EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, /* - * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. + * Early Firmware Selection ver.2. Enabled by VBOOT_EFS2 config option. * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should * be sent to RO to be precise. */ diff --git a/src/include/rules.h b/src/include/rules.h index d30b2b8..6ebb37e 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -63,10 +63,11 @@
/* * NOTE: "verstage" code may either run as a separate stage or linked into the - * bootblock/romstage, depending on the setting of CONFIG_SEPARATE_VERSTAGE. The - * ENV_SEPARATE_VERSTAGE macro will only return true for "verstage" code when - * CONFIG_SEPARATE_VERSTAGE=y, otherwise that code will have ENV_BOOTBLOCK or - * ENV_ROMSTAGE set (depending on the CONFIG_VBOOT_STARTS_IN_... options). + * bootblock/romstage, depending on the setting of the VBOOT_SEPARATE_VERSTAGE + * kconfig option. The ENV_SEPARATE_VERSTAGE macro will only return true for + * "verstage" code when CONFIG(VBOOT_SEPARATE_VERSTAGE) is true, otherwise that + * code will have ENV_BOOTBLOCK or ENV_ROMSTAGE set (depending on the + * "VBOOT_STARTS_IN_"... kconfig options). */ #elif defined(__VERSTAGE__) #define ENV_DECOMPRESSOR 0 diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index b54619d..0a7a822 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -8,7 +8,7 @@
struct romstage_handoff { /* Indicate if the current boot is an S3 resume. If - * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is + * CONFIG_RELOCATABLE_RAMSTAGE is enabled the chipset code is * responsible for initializing this variable. Otherwise, ramstage * will be re-loaded from cbfs (which can be slower since it lives * in flash). */ diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 6cfce43..4a791ef 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -27,11 +27,11 @@ /* * +-------------------------+ Top of RAM (aligned) * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE + * | code and data | Length: CONFIG_SMM_TSEG_SIZE * | (TSEG) | * +-------------------------+ SMM base (aligned) * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | Chipset Reserved Memory | Length: Multiple of CONFIG_SMM_TSEG_SIZE * | | * +-------------------------+ top_of_ram (aligned) * | |
-
Angel Pons (Code Review) -
Christian Walter (Code Review)
-
Furquan Shaikh (Code Review)
-
Martin Roth (Code Review)
-
Patrick Georgi (Code Review)