Ravishankar Sarawadi (ravishankar.sarawadi@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16587
-gerrit
commit af331d3a038578f23cd7b77115354dc89cb7c717 Author: Ravi Sarawadi ravishankar.sarawadi@intel.com Date: Fri Sep 9 14:08:50 2016 -0700
[WIP]soc/apollolake: Restore MSRs after S3 resume
Restore necessary MSRs after suspend cycle.
BUG=chrome-os-partner:56922 BRANCH=None
TEST=Use iotools rdmsr and 'powertop' to check Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com
Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 --- src/soc/intel/apollolake/cpu.c | 23 ++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/cpu.h | 3 +++ 2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 86fe3e1..36d765c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,11 +25,32 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <reg_script.h> #include <soc/cpu.h> #include <soc/smm.h>
+ +static const struct reg_script core_msr_script[] = { + + REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, 0x8472), + REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, 0x50414), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_SCRIPT_END +}; + +static void soc_core_init(device_t cpu) +{ + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(cpu)); + printk(BIOS_DEBUG, "Init Apollolake core.\n"); + + /* Set core MSRs */ + reg_script_run(core_msr_script); +} + static struct device_operations cpu_dev_ops = { - .init = DEVICE_NOOP, + .init = soc_core_init, };
static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 8887c17..ad2eba4 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -38,6 +38,9 @@ void apollolake_init_cpus(struct device *dev); #define PREFETCH_L1_DISABLE (1 << 0) #define PREFETCH_L2_DISABLE (1 << 2)
+#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_POWER_CTL 0x1fc
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f