Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning

[Bao Zheng (Code Review)]

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59918

to look at the new patch set (#2).

Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
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soc/amd/cezanne: FSP: Add UPD entry for eDP tuning

BUG=b:203061533

Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao 
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fsp_m_params.c
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
3 files changed, 31 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59918/2