Change in coreboot[master]: sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44413 )

Change subject: sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'
......................................................................

sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'

Change-Id: I1a70eea8c4f835e5673e75282c9cecb24b150e3d
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/lynxpoint/early_pch.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44413/1

diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index e74fdc5..85f9f33 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/smbus_host.h>
+#include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <elog.h>
 #include "pch.h"
@@ -57,7 +58,7 @@
 {
    printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
    RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
+	write_pmbase16(0x60 | 0x08, (1 << 11));	/* halt timer */
    printk(BIOS_DEBUG, " done.\n");
 }

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44413 )

Change subject: sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44413 )

Change subject: sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'
......................................................................

sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'

Change-Id: I1a70eea8c4f835e5673e75282c9cecb24b150e3d
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44413
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Georgi 
---
M src/southbridge/intel/lynxpoint/early_pch.c
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved

diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index e74fdc5..85f9f33 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/smbus_host.h>
+#include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <elog.h>
 #include "pch.h"
@@ -57,7 +58,7 @@
 {
    printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
    RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
+	write_pmbase16(0x60 | 0x08, (1 << 11));	/* halt timer */
    printk(BIOS_DEBUG, " done.\n");
 }