Patch set updated for coreboot: nb/x4x: Do not enable IGD when not supported

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18515

-gerrit

commit 19906decddfce25a0cd41e3d9edab75d53e7ff35
Author: Arthur Heymans 
Date:   Mon Feb 27 20:14:21 2017 +0100

nb/x4x: Do not enable IGD when not supported

According to "Intel ® 4 Series Chipset Family datasheet" in the
    description about GGC and DEVEN, CAPID0 bit48 is said to reflect the
    presence of an internal graphic device. This would allow the P43 and
    P45 chipset variants to work.

Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
    Signed-off-by: Arthur Heymans 
---
 src/northbridge/intel/x4x/early_init.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 7d6afc9..33fc797 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -54,16 +54,22 @@ void x4x_early_init(void)
    pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
    pci_write_config8(d0f0, D0F0_PAM(6), 0x33);

-	/* Enable internal GFX */
-	pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
-	/* Set preallocated IGD size from cmos */
-	u8 gfxsize;
-
-	if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
-		/* 6 for 64MB, default if not set in cmos */
-		gfxsize = 6;
+	if (pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32))) {
+		/* Enable internal GFX */
+		pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
+		/* Set preallocated IGD size from cmos */
+		u8 gfxsize;
+
+		if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
+			/* 6 for 64MB, default if not set in cmos */
+			gfxsize = 6;
+		}
+		pci_write_config16(d0f0, D0F0_GGC,
+				0x0100 | ((gfxsize + 1) << 4));
+	} else { /* Does not feature internal graphics */
+		pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
+		pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
    }
-	pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4));
 }

static void init_egress(void)