Change in coreboot[master]: soc/intel/skylake: Enable HDA depending on devicetree configuration
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43866 )
Change subject: soc/intel/skylake: Enable HDA depending on devicetree configuration ......................................................................
soc/intel/skylake: Enable HDA depending on devicetree configuration
Currently HDA gets enabled by the option EnableAzalia, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 24 files changed, 6 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/43866/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index a0c746b..2ffc4cb 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -46,7 +46,6 @@ register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index a19d9f4..44776a2 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -36,7 +36,6 @@ register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "PchHdaVcType" = "Vc1"
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index c32c2af..a2399ea 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ register "dptf_enable" = "1"
# FSP Configuration - register "EnableAzalia" = "1" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 0ae1548..bc35337 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -39,7 +39,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index c8fd334..cf8df89 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -70,7 +70,6 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 6c5ea30..a3af3d8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -41,7 +41,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ce61b0d..92edcf8 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -45,7 +45,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index f166682..0ca46c3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -35,7 +35,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 9094e67..a48d8d3 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -34,7 +34,6 @@ register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b32e4f9..64fc064 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -35,7 +35,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 6e2fd67..4f2cd5b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -40,7 +40,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 636335a..f4901e4 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -45,7 +45,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ef754a3..54b39ac 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -35,7 +35,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 4fbe677..399f361 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -166,7 +166,7 @@ device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b7b569d7..cfb50e3 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/skylake
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "0" @@ -126,6 +125,7 @@ device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.6 off end # SDCard + device pci 1f.3 on end # Intel HDA device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index a269d01..5cfb10d 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -7,7 +7,6 @@ register "gen2_dec" = "0x000c0201"
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "HeciEnabled" = "0" @@ -134,5 +133,6 @@ device pnp 0c31.0 on end end end # LPC Interface + device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 56a3347..d54581b 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -24,7 +24,6 @@ register "dptf_enable" = "1"
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index defb5e3..100ce89 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -18,7 +18,6 @@ register "speed_shift_enable" = "1"
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 542f2645..fc91459 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -47,7 +47,6 @@ register "SataPortsDevSlp[1]" = "0" register "SataPortsDevSlp[2]" = "0" register "SataSpeedLimit" = "2" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index fb78b00..53b8326 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -36,7 +36,6 @@ register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 43c70de..9b9a83d 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -52,7 +52,6 @@ register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 38b02fe..c55d168 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -32,7 +32,6 @@ register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index fcc8840..38b9c1f 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -272,7 +272,9 @@ dev = pcidev_path_on_root(PCH_DEVFN_ISH); params->PchIshEnable = dev ? dev->enabled : 0;
- params->PchHdaEnable = config->EnableAzalia; + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + params->PchHdaEnable = dev ? dev->enabled : 0; + params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8906efd0..f5b049f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -170,7 +170,6 @@ u8 SataSpeedLimit;
/* Audio related */ - u8 EnableAzalia; u8 DspEnable;
/* HDA Virtual Channel Type Select */
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43866 )
Change subject: soc/intel/skylake: Enable HDA depending on devicetree configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43866/2/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/43866/2/src/soc/intel/skylake/chip.... PS2, Line 278: params->PchHdaVcType = config->PchHdaVcType; : params->PchHdaIoBufferOwnership = config->IoBufferOwnership; : params->PchHdaDspEnable = config->DspEnable; : these depend on PchHdaEnable
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43866 )
Change subject: soc/intel/skylake: Enable HDA depending on devicetree configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43866/2/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/43866/2/src/soc/intel/skylake/chip.... PS2, Line 278: params->PchHdaVcType = config->PchHdaVcType; : params->PchHdaIoBufferOwnership = config->IoBufferOwnership; : params->PchHdaDspEnable = config->DspEnable; :
these depend on PchHdaEnable
oops, Device4Enable not, ofc
Hello build bot (Jenkins), Michał Żygowski, Frans Hendriks, Patrick Rudolph, Wim Vervoorn, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43866
to look at the new patch set (#5).
Change subject: soc/intel/skylake: Enable HDA depending on devicetree configuration ......................................................................
soc/intel/skylake: Enable HDA depending on devicetree configuration
Currently HDA gets enabled by the option EnableAzalia, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 24 files changed, 6 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/43866/5
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43866 )
Change subject: soc/intel/skylake: Enable HDA depending on devicetree configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43866/2/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/43866/2/src/soc/intel/skylake/chip.... PS2, Line 278: params->PchHdaVcType = config->PchHdaVcType; : params->PchHdaIoBufferOwnership = config->IoBufferOwnership; : params->PchHdaDspEnable = config->DspEnable; :
oops, Device4Enable not, ofc
This change is not intended to change the logic of this code.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43866 )
Change subject: soc/intel/skylake: Enable HDA depending on devicetree configuration ......................................................................
Patch Set 5: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43866 )
Change subject: soc/intel/skylake: Enable HDA depending on devicetree configuration ......................................................................
soc/intel/skylake: Enable HDA depending on devicetree configuration
Currently HDA gets enabled by the option EnableAzalia, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 24 files changed, 6 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 937986e..d4ab530 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -46,7 +46,6 @@ register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 36a73b5..fae925f 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -36,7 +36,6 @@ register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "PchHdaVcType" = "Vc1"
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index a6689e5..8621663 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ register "dptf_enable" = "1"
# FSP Configuration - register "EnableAzalia" = "1" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 3c33b8c..5e927b4 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -39,7 +39,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 888e111..ac3ee8b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -70,7 +70,6 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 1dd8dbc..1e1b8e8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -41,7 +41,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index fafd0c1..432ef99 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -45,7 +45,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 7c5c332..2dc0703 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -35,7 +35,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 19a8cf7..8e1f954 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -34,7 +34,6 @@ register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index dc133b6..0a67d4d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -35,7 +35,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index cc72e77..8959a29 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -40,7 +40,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index ada2be8..54faf47 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -45,7 +45,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index b0ddef6..777c521 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -35,7 +35,6 @@ register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 0262498..0b1ba1d 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -157,7 +157,7 @@ device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b7b569d7..cfb50e3 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/skylake
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "0" @@ -126,6 +125,7 @@ device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.6 off end # SDCard + device pci 1f.3 on end # Intel HDA device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index a269d01..5cfb10d 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -7,7 +7,6 @@ register "gen2_dec" = "0x000c0201"
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "HeciEnabled" = "0" @@ -134,5 +133,6 @@ device pnp 0c31.0 on end end end # LPC Interface + device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 283c0a1..aebda85 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -24,7 +24,6 @@ register "dptf_enable" = "1"
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index a8066d5..2a0558e 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -18,7 +18,6 @@ register "speed_shift_enable" = "1"
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 578abf0..a58e169 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -47,7 +47,6 @@ register "SataPortsDevSlp[1]" = "0" register "SataPortsDevSlp[2]" = "0" register "SataSpeedLimit" = "2" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d66a38c..9071a7b 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -36,7 +36,6 @@ register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index a181352..5aa51d3 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -52,7 +52,6 @@ register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 1efb399..01aec8b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -32,7 +32,6 @@ register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a73aa8d..562d791 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -272,7 +272,9 @@ dev = pcidev_path_on_root(PCH_DEVFN_ISH); params->PchIshEnable = dev ? dev->enabled : 0;
- params->PchHdaEnable = config->EnableAzalia; + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + params->PchHdaEnable = dev ? dev->enabled : 0; + params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 3f55c18..fc86cfd 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -157,7 +157,6 @@ u8 SataSpeedLimit;
/* Audio related */ - u8 EnableAzalia; u8 DspEnable;
/* HDA Virtual Channel Type Select */
-
Felix Singer (Code Review) -
Michael Niewöhner (Code Review)