[S] Change in coreboot[master]: soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMC

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75822?usp=email )

Change subject: soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMC
......................................................................

soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMC

This patch disables the ACPI PM timer which is necessary for XTAL OSC
shutdown. Also, disabling ACPI PM timer switches off TCO.

BUG=b:274744845
TEST=Able to boot and verify S0ix is working even with EC reset and
cold boot scenarios.

w/o this cl:
> iotools mmio_read32 0xfe4018fc

0x0

w/ this cl:
> iotools mmio_read32 0xfe4018fc

0x2

Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75822
Tested-by: build bot (Jenkins) 
Reviewed-by: Kapil Porwal 
---
M src/soc/intel/meteorlake/include/soc/iomap.h
M src/soc/intel/meteorlake/include/soc/pm.h
M src/soc/intel/meteorlake/pmc.c
M src/soc/intel/meteorlake/pmutil.c
4 files changed, 14 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Kapil Porwal: Looks good to me, approved

diff --git a/src/soc/intel/meteorlake/include/soc/iomap.h b/src/soc/intel/meteorlake/include/soc/iomap.h
index a2df40c..3efe400 100644
--- a/src/soc/intel/meteorlake/include/soc/iomap.h
+++ b/src/soc/intel/meteorlake/include/soc/iomap.h
@@ -25,6 +25,9 @@

#define HPET_BASE_ADDRESS	0xfed00000

+#define IOE_PWRM_BASE_ADDRESS	0xfe400000
+#define IOE_PWRM_BASE_SIZE	0x10000
+
 #define PCH_PWRM_BASE_ADDRESS	0xfe000000
 #define PCH_PWRM_BASE_SIZE	0x10000

diff --git a/src/soc/intel/meteorlake/include/soc/pm.h b/src/soc/intel/meteorlake/include/soc/pm.h
index c486232..7474cdd 100644
--- a/src/soc/intel/meteorlake/include/soc/pm.h
+++ b/src/soc/intel/meteorlake/include/soc/pm.h
@@ -150,6 +150,9 @@
 /* Get base address PMC memory mapped registers. */
 uint8_t *pmc_mmio_regs(void);

+/* Get base address IOE.PMC memory mapped registers. */
+uint8_t *ioe_pmc_mmio_regs(void);
+
 /* Get base address of TCO I/O registers. */
 uint16_t smbus_tco_regs(void);

diff --git a/src/soc/intel/meteorlake/pmc.c b/src/soc/intel/meteorlake/pmc.c
index bdd7a3b..9a2c982 100644
--- a/src/soc/intel/meteorlake/pmc.c
+++ b/src/soc/intel/meteorlake/pmc.c
@@ -157,8 +157,10 @@
     * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
     * Disabling ACPI PM timer also switches off TCO
     */
-	if (!CONFIG(USE_PM_ACPI_TIMER))
+	if (!CONFIG(USE_PM_ACPI_TIMER)) {
    	setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
+		setbits8(ioe_pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
+	}
 }

static void pm1_enable_pwrbtn_smi(void *unused)
diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c
index 8b377c0..abe9550 100644
--- a/src/soc/intel/meteorlake/pmutil.c
+++ b/src/soc/intel/meteorlake/pmutil.c
@@ -134,6 +134,11 @@
    return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 }

+uint8_t *ioe_pmc_mmio_regs(void)
+{
+	return (void *)(uintptr_t)IOE_PWRM_BASE_ADDRESS;
+}
+
 uintptr_t soc_read_pmc_base(void)
 {
    return (uintptr_t)pmc_mmio_regs();