Patch set updated for coreboot: d7203bc mc146818rtc: Disable read_option on non-romcc code
Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4824
-gerrit
commit d7203bcffda2ac9179c0f8b69d572362203f15d0 Author: Vladimir Serbinenko phcoder@gmail.com Date: Sun Jan 26 20:25:49 2014 +0100
mc146818rtc: Disable read_option on non-romcc code
Do not commit.
Change-Id: I903aab9490bd405b0dbbbe23d2ef1db29845392b Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/cpu/amd/dualcore/dualcore.c | 9 +++--- src/cpu/amd/model_10xxx/init_cpus.c | 7 +++-- src/cpu/amd/model_fxx/init_cpus.c | 11 ++++--- src/cpu/amd/quadcore/quadcore.c | 9 +++--- src/include/pc80/mc146818rtc.h | 5 ++++ src/lib/coreboot_table.c | 3 -- src/mainboard/getac/p470/romstage.c | 8 +++-- src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 - src/mainboard/kontron/986lcd-m/romstage.c | 26 ++++++++++++---- src/mainboard/msi/ms7135/romstage.c | 13 ++++---- src/mainboard/roda/rk886ex/romstage.c | 8 +++-- src/mainboard/samsung/lumpy/romstage.c | 1 - src/mainboard/samsung/stumpy/romstage.c | 15 ++++------ src/northbridge/amd/amdk8/coherent_ht.c | 9 +++--- src/northbridge/amd/amdk8/raminit.c | 22 ++++++++++---- src/northbridge/amd/amdk8/raminit_f.c | 39 ++++++++++++------------ src/northbridge/intel/sandybridge/raminit.c | 46 +++++++++++++++++++++-------- 17 files changed, 145 insertions(+), 87 deletions(-)
diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 69ce56a..5fe101e 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -2,9 +2,6 @@
#include "cpu/amd/dualcore/dualcore_id.c" #include <pc80/mc146818rtc.h> -#if CONFIG_HAVE_OPTION_TABLE -#include "option_table.h" -#endif
static inline unsigned get_core_num_in_bsp(unsigned nodeid) { @@ -48,8 +45,12 @@ static inline void start_other_cores(void) { unsigned nodes; unsigned nodeid; + u8 multi_core; + + if (get_option(&multi_core, "multi_core") != CB_SUCCESS) + multi_core = 0; /* Enabled. */
- if (read_option(multi_core, 0)) { + if (multi_core) { return; // disable multi_core }
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 10c0c8a..2567610 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -67,12 +67,15 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, u32 nb_cfg_54; int i, j; u32 ApicIdCoreIdSize; + u8 multi_core; + + if (get_option(&multi_core, "multi_core") != CB_SUCCESS) + multi_core = 0; /* Enabled. */
/* get_nodes define in ht_wrapper.c */ nodes = get_nodes();
- if (!CONFIG_LOGICAL_CPUS || - read_option(multi_core, 0) != 0) { // 0 means multi core + if (!CONFIG_LOGICAL_CPUS || multi_core != 0) { // 0 means multi core disable_siblings = 1; } else { disable_siblings = 0; diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 12d3a95..75b45e2 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -1,9 +1,5 @@ #include "cpu/amd/car/post_cache_as_ram.c"
-#if CONFIG_HAVE_OPTION_TABLE -#include "option_table.h" -#endif - typedef void (*process_ap_t) (u32 apicid, void *gp);
//core_range = 0 : all cores @@ -22,12 +18,15 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, u32 e0_later_single_core; u32 nb_cfg_54; int i, j; + u8 multi_core; + + if (get_option(&multi_core, "multi_core") != CB_SUCCESS) + multi_core = 0; /* Enabled. */
/* get_nodes define in in_coherent_ht.c */ nodes = get_nodes();
- if (!CONFIG_LOGICAL_CPUS || - read_option(multi_core, 0) != 0) { // 0 means multi core + if (!CONFIG_LOGICAL_CPUS || multi_core != 0) { // 0 means multi core disable_siblings = 1; } else { disable_siblings = 0; diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index feff3e1..6f60c2f 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -20,9 +20,6 @@ #include <console/console.h> #include <pc80/mc146818rtc.h> #include <northbridge/amd/amdht/ht_wrapper.c> -#if CONFIG_HAVE_OPTION_TABLE -#include "option_table.h" -#endif
#include "cpu/amd/quadcore/quadcore_id.c"
@@ -80,9 +77,13 @@ static void start_other_cores(void) { u32 nodes; u32 nodeid; + u8 multi_core; + + if (get_option(&multi_core, "multi_core") != CB_SUCCESS) + multi_core = 0; /* Enabled. */
// disable multi_core - if (read_option(multi_core, 0) != 0) { + if (multi_core != 0) { printk(BIOS_DEBUG, "Skip additional core init\n"); return; } diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index fd40308..11aed88 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -188,8 +188,12 @@ static inline enum cb_err get_option(void *dest __attribute__((unused)), #else #include <drivers/pc80/mc146818rtc_early.c> #endif + +#if defined(__ROMCC__) #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default)) +#endif
+#if defined(__ROMCC__) #if CONFIG_CMOS_POST #if CONFIG_USE_OPTION_TABLE # include "option_table.h" @@ -201,6 +205,7 @@ static inline enum cb_err get_option(void *dest __attribute__((unused)), # error "Must define CONFIG_CMOS_POST_OFFSET" # endif #endif +#endif
/* * 0 = Bank Select Magic diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index f433e86..22991cd 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -30,9 +30,6 @@ #include <cbfs.h> #include <cbmem.h> #include <memrange.h> -#if CONFIG_USE_OPTION_TABLE -#include <option_table.h> -#endif #if CONFIG_CHROMEOS #if CONFIG_GENERATE_ACPI_TABLES #include <arch/acpi.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a081a8a..f96fe2c 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -33,7 +33,6 @@ #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -#include "option_table.h"
void setup_ich7_gpios(void) { @@ -82,7 +81,12 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { int lpt_en = 0; - if (read_option(lpt, 0) != 0) { + u8 val; + + if (get_option(&val, "lpt") != CB_SUCCESS) + val = 0; + + if (val != 0) { lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8e109c5..770da97 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -35,7 +35,6 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include "option_table.h" #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 549facd..22a7c23 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -29,7 +29,6 @@ #include <cpu/x86/lapic.h> #include "superio/winbond/w83627thg/w83627thg.h" #include <pc80/mc146818rtc.h> -#include "option_table.h" #include <console/console.h> #include <cpu/x86/bist.h> #include "superio/winbond/w83627thg/early_serial.c" @@ -58,7 +57,12 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { int lpt_en = 0; - if (read_option(lpt, 0) != 0) { + u8 val; + + if (get_option(&val, "lpt") != CB_SUCCESS) + val = 0; + + if (val != 0) { lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ @@ -222,23 +226,35 @@ static void rcba_config(void) * routing. */ int port_shuffle = 0; + u8 val;
/* Disable unused devices */ reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
- if (read_option(ethernet1, 0) != 0) { + if (get_option(&val, "ethernet1") != CB_SUCCESS) + val = 0; + + if (val != 0) { printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n"); reg32 |= FD_PCIE1; } - if (read_option(ethernet2, 0) != 0) { + + if (get_option(&val, "ethernet2") != CB_SUCCESS) + val = 0; + + if (val != 0) { printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n"); reg32 |= FD_PCIE2; } else { if (reg32 & FD_PCIE1) port_shuffle = 1; } - if (read_option(ethernet3, 0) != 0) { + + if (get_option(&val, "ethernet3") != CB_SUCCESS) + val = 0; + + if (val != 0) { printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n"); reg32 |= FD_PCIE3; } else { diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index ebe2526..ccf44c7 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -45,10 +45,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h>
-#if CONFIG_HAVE_OPTION_TABLE -#include "option_table.h" -#endif - #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -69,7 +65,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void ms7135_set_ram_voltage(void) { u8 b; - b = read_option(ram_voltage, 0); + + if (get_option(&b, "ram_voltage") != CB_SUCCESS) + b = 0; + if (b > 4) /* default if above 2.70v */ b = 0; printk(BIOS_INFO, "setting RAM voltage %08x\n", b); @@ -79,7 +78,9 @@ static void ms7135_set_ram_voltage(void) static void ms7135_set_nf4_voltage(void) { u8 b; - b = read_option(nf4_voltage, 0); + if (get_option(&b, "nf4_voltage") != CB_SUCCESS) + b = 0; + if (b > 2) /* default if above 1.60v */ b = 0; b |= 0x10; diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ad323f5..2ed65ff 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -35,7 +35,6 @@ #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -#include "option_table.h"
void setup_ich7_gpios(void) { @@ -69,7 +68,12 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { int lpt_en = 0; - if (read_option(lpt, 0) != 0) { + u8 val; + + if (get_option(&val, "lpt") != CB_SUCCESS) + val = 0; + + if (val != 0) { lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 9933459..0c3fa46 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -38,7 +38,6 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> -#include "option_table.h" #include "gpio.h" #if CONFIG_CONSOLE_SERIAL8250 #include "superio/smsc/lpc47n207/lpc47n207.h" diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index e5b55b5..df10b3f 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -48,13 +48,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #endif
-/* Stumpy USB Reset Disable defined in cmos.layout */ -#if CONFIG_USE_OPTION_TABLE -#include "option_table.h" -#define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3) -#else -#define CMOS_USB_RESET_DISABLE (400 >> 3) -#endif #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */
static void pch_enable_lpc(void) @@ -293,7 +286,11 @@ void main(unsigned long bist) * controller reset in case the kernel can tolerate * the device power loss better in the future. */ - u8 magic = cmos_read(CMOS_USB_RESET_DISABLE); + u8 magic; + + if (get_option (&magic, "stumpy_usb_reset_disable") + != CB_SUCCESS) + magic = 0;
if (magic == USB_RESET_DISABLE_MAGIC) { printk(BIOS_DEBUG, "USB Controller Reset Disabled\n"); @@ -303,7 +300,7 @@ void main(unsigned long bist) } } else { /* Ensure USB reset on resume is enabled at boot */ - cmos_write(0, CMOS_USB_RESET_DISABLE); + set_option("stumpy_usb_reset_disable", &(u8[]){ 0x00 }); }
post_code(0x39); diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 22d74c2..b79d43c 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -69,9 +69,6 @@ #include <stdlib.h> #include <arch/io.h> #include <pc80/mc146818rtc.h> -#if CONFIG_HAVE_OPTION_TABLE -#include "option_table.h" -#endif
#include "amdk8.h"
@@ -1598,8 +1595,12 @@ static void coherent_ht_finalize(unsigned nodes) #endif #if CONFIG_LOGICAL_CPUS unsigned total_cpus; + u8 multi_core; + + if (get_option(&multi_core, "multi_core") != CB_SUCCESS) + multi_core = 0; /* Enabled. */
- if (read_option(multi_core, 0) == 0) { /* multi_core */ + if (multi_core == 0) { /* multi_core */ total_cpus = verify_dualcore(nodes); } else { diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index e4fe3df..0247758 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -11,9 +11,6 @@ #include <reset.h> #include "raminit.h" #include "amdk8.h" -#if CONFIG_HAVE_OPTION_TABLE -#include "option_table.h" -#endif
#include <arch/early_variables.h> struct sys_info sysinfo_car CAR_GLOBAL; @@ -546,13 +543,17 @@ static void sdram_set_registers(const struct mem_controller *ctrl) static void hw_enable_ecc(const struct mem_controller *ctrl) { uint32_t dcl, nbcap; + u8 ecc_memory; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_DimmEccEn; if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (read_option(ECC_memory, 1) == 0) { + if (get_option(&ecc_memory, "ECC_memory") != CB_SUCCESS) + ecc_memory = 1; + + if (ecc_memory == 0) { dcl &= ~DCL_DimmEccEn; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); @@ -1103,8 +1104,12 @@ static unsigned long memory_end_k(const struct mem_controller *ctrl, int max_nod static void order_dimms(const struct mem_controller *ctrl) { unsigned long tom_k, base_k; + u8 val; + + if (get_option(&val, "interleave_chip_selects") != CB_SUCCESS) + val = 1;
- if (read_option(interleave_chip_selects, 1) != 0) { + if (val != 0) { tom_k = interleave_chip_selects(ctrl); } else { printk(BIOS_DEBUG, "Interleaving disabled\n"); @@ -1582,6 +1587,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; + u8 val;
static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; static const unsigned char cycle_time_at_freq[] = { @@ -1603,7 +1609,11 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * memset(cl_at_freq, 0x00, (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); - max_freq_bios = read_option(max_mem_clock, 0); + + if (get_option(&val, "max_mem_clock") != CB_SUCCESS) + val = 0; + + max_freq_bios = val; if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) memset(cl_at_freq, 0x00, max_freq_bios); for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 9c99250..c376e2c 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -29,9 +29,6 @@ #include "raminit.h" #include "f.h" #include <spd_ddr2.h> -#if CONFIG_HAVE_OPTION_TABLE -#include "option_table.h" -#endif
#if CONFIG_DEBUG_RAM_SETUP #define printk_raminit(args...) printk(BIOS_DEBUG, args) @@ -1112,7 +1109,12 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, * and if so count them. */ #if defined(CMOS_VSTART_interleave_chip_selects) - if (read_option(interleave_chip_selects, 1) == 0) + u8 val; + + if (get_option(&val, "interleave_chip_selects") != CB_SUCCESS) + val = 1; + + if (val == 0) return 0; #else #if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || !CONFIG_INTERLEAVE_CHIP_SELECTS @@ -1808,17 +1810,18 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ -#ifdef CMOS_VSTART_max_mem_clock - read_option(max_mem_clock, 0) -#else + + u8 max_mem_clock; + + if (get_option(&max_mem_clock, "max_mem_clock") != CB_SUCCESS) { #if defined(CONFIG_MAX_MEM_CLOCK) - CONFIG_MAX_MEM_CLOCK + max_mem_clock = CONFIG_MAX_MEM_CLOCK; #else - 0 // use DDR400 as default -#endif + max_mem_clock = 0; /* use DDR400 as default */ #endif - ]; + } + + bios_cycle_time = min_cycle_times[max_mem_clock];
if (bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; @@ -2370,6 +2373,7 @@ static void set_ecc(const struct mem_controller *ctrl, { int i; int value; + u8 ecc_memory;
uint32_t dcl, nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); @@ -2378,15 +2382,12 @@ static void set_ecc(const struct mem_controller *ctrl, if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } -#ifdef CMOS_VSTART_ECC_memory - if (read_option(ECC_memory, 1) == 0) { + if (get_option(&ecc_memory, "ECC_memory") != CB_SUCCESS) + ecc_memory = 1; + + if (ecc_memory == 0) { dcl &= ~DCL_DimmEccEn; } -#else // CMOS_VSTART_ECC_memory not defined -#if !CONFIG_ECC_MEMORY - dcl &= ~DCL_DimmEccEn; -#endif -#endif pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
meminfo->is_ecc = 1; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b9c3839..7e18935 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -41,14 +41,9 @@
/* * MRC scrambler seed offsets should be reserved in - * mainboard cmos.layout and not covered by checksum. + * mainboard cmos.layout */ -#if CONFIG_USE_OPTION_TABLE -#include "option_table.h" -#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) -#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) -#define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) -#else +#if !CONFIG_USE_OPTION_TABLE #define CMOS_OFFSET_MRC_SEED 152 #define CMOS_OFFSET_MRC_SEED_S3 156 #define CMOS_OFFSET_MRC_SEED_CHK 160 @@ -86,11 +81,10 @@ void save_mrc_data(struct pei_data *pei_data) #endif
/* Save the MRC seed values to CMOS */ - cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); + printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
- cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
@@ -101,8 +95,16 @@ void save_mrc_data(struct pei_data *pei_data) sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2);
+#if CONFIG_USE_OPTION_TABLE + set_option("mrc_scrambler_seed", &pei_data->scrambler_seed); + set_option("mrc_scrambler_seed_s3", &pei_data->scrambler_seed_s3); + set_option("mrc_scrambler_seed_chm", &checksum); +#else + cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); + cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); +#endif }
static void prepare_mrc_cache(struct pei_data *pei_data) @@ -115,13 +117,34 @@ static void prepare_mrc_cache(struct pei_data *pei_data) pei_data->mrc_input_len = 0;
/* Read scrambler seeds from CMOS */ +#if CONFIG_USE_OPTION_TABLE + if (get_option("mrc_scrambler_seed", &pei_data->scrambler_seed) + != CB_SUCCESS + || get_option("mrc_scrambler_seed_s3", + &pei_data->scrambler_seed_s3) != CB_SUCCESS + || get_option("mrc_scrambler_seed_chm", + &seed_checksum) != CB_SUCCESS) { + printk(BIOS_ERR, "%s: error retrieving seed\n", __func__); + pei_data->scrambler_seed = 0; + pei_data->scrambler_seed_s3 = 0; + return; + } + printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from option\n", + pei_data->scrambler_seed); + + printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from option\n", + pei_data->scrambler_seed_s3); +#else pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); + pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); + seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); + seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
- pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); +#endif
/* Compute seed checksum and compare */ c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, @@ -130,9 +153,6 @@ static void prepare_mrc_cache(struct pei_data *pei_data) sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2);
- seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); - seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; - if (checksum != seed_checksum) { printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); pei_data->scrambler_seed = 0;
-
Vladimir Serbinenko