[XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz

[Kiwi Liu (Code Review)]

Attention is currently required from: Hung-Te Lin, Mengqi Zhang, Paul Menzel, Yidi Lin, Yu-Ping Wu.

Kiwi Liu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )

Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
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Patch Set 13:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84298/comment/f4b5f7af_3f66e14e?usp... :
PS12, Line 11: When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and the frequency division value to 125. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/125=3.2MHz. When we set the source clock frequency correctly, we can get the correct frequency division value, and then get the correct clock output.
> Please add a blank line between paragraphs, and re-flow it for 72 characters per line.

Done