Change in coreboot[master]: soc/mediatek/mt8183: fine tune the phy timing

[jitao shi (Code Review)]

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36222 )

Change subject: soc/mediatek/mt8183: fine tune the phy timing
......................................................................

soc/mediatek/mt8183: fine tune the phy timing

For fix MIPI D-PHY test fail,
Ths-prepare is less than LimitMin spec.
And enlarge TEOT margin.

BUG=b:138344447
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi 
---
M src/soc/mediatek/common/dsi.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/36222/1

diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c
index 679bec8..2b4fac7 100644
--- a/src/soc/mediatek/common/dsi.c
+++ b/src/soc/mediatek/common/dsi.c
@@ -81,9 +81,9 @@
    memset(phy_timing, 0, sizeof(*phy_timing));

phy_timing->lpx = DIV_ROUND_UP(60, cycle_time);
-	phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time);
+	phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time);
    phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time);
-	phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time);
+	phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time);

phy_timing->ta_go = 4U * phy_timing->lpx;
    phy_timing->ta_sure = 3U * phy_timing->lpx / 2U;

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36222 )

Change subject: soc/mediatek/mt8183: fine tune the phy timing
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/36222/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36222/1//COMMIT_MSG@9 
PS1, Line 9: For fix MIPI D-PHY test fail,
           : Ths-prepare is less than LimitMin spec.
           : And enlarge TEOT margin.
           : 
Not sure if this what you mean, but what about:

To fix MIPI D-PHY test failure, the hs-prepare should be less than LimitMin from spec, and we have to enlarge TEOT margin.

https://review.coreboot.org/c/coreboot/+/36222/1//COMMIT_MSG@14 
PS1, Line 14: none
kukui

[jitao shi (Code Review)]

Hello Yu-Ping Wu, Julius Werner, Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36222

to look at the new patch set (#2).

Change subject: soc/mediatek/mt8183: fine tune the phy timing
......................................................................

soc/mediatek/mt8183: fine tune the phy timing

To fix MIPI D-PHY test failure, the hs-prepare should be less than
LimitMin from spec, and we have to enlarge TEOT margin.

BUG=b:138344447
BRANCH=none
TEST=Boots correctly on kukui

Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi 
---
M src/soc/mediatek/common/dsi.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/36222/2

[jitao shi (Code Review)]

jitao shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36222 )

Change subject: soc/mediatek/mt8183: fine tune the phy timing
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/36222/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36222/1//COMMIT_MSG@9 
PS1, Line 9: For fix MIPI D-PHY test fail,
           : Ths-prepare is less than LimitMin spec.
           : And enlarge TEOT margin.
           :
> Not sure if this what you mean, but what about: […]

Done

https://review.coreboot.org/c/coreboot/+/36222/1//COMMIT_MSG@14 
PS1, Line 14: none
> kukui

Done

[jitao shi (Code Review)]

Hello Yu-Ping Wu, Julius Werner, Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36222

to look at the new patch set (#3).

Change subject: soc/mediatek/mt8183: fine tune the phy timing
......................................................................

soc/mediatek/mt8183: fine tune the phy timing

To fix MIPI D-PHY test failure, the hs-prepare should be less than
LimitMin from spec, and we have to enlarge TEOT margin.

BUG=b:138344447
BRANCH=kukui
TEST=Boots correctly on kukui

Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi 
---
M src/soc/mediatek/common/dsi.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/36222/3

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36222 )

Change subject: soc/mediatek/mt8183: fine tune the phy timing
......................................................................

Patch Set 3: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36222 )

Change subject: soc/mediatek/mt8183: fine tune the phy timing
......................................................................

soc/mediatek/mt8183: fine tune the phy timing

To fix MIPI D-PHY test failure, the hs-prepare should be less than
LimitMin from spec, and we have to enlarge TEOT margin.

BUG=b:138344447
BRANCH=kukui
TEST=Boots correctly on kukui

Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222
Tested-by: build bot (Jenkins) 
Reviewed-by: Hung-Te Lin 
---
M src/soc/mediatek/common/dsi.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved

diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c
index 679bec8..2b4fac7 100644
--- a/src/soc/mediatek/common/dsi.c
+++ b/src/soc/mediatek/common/dsi.c
@@ -81,9 +81,9 @@
    memset(phy_timing, 0, sizeof(*phy_timing));

phy_timing->lpx = DIV_ROUND_UP(60, cycle_time);
-	phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time);
+	phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time);
    phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time);
-	phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time);
+	phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time);

phy_timing->ta_go = 4U * phy_timing->lpx;
    phy_timing->ta_sure = 3U * phy_timing->lpx / 2U;