Change in coreboot[master]: soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S

[Tim Crawford (Code Review)]

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https://review.coreboot.org/c/coreboot/+/56867

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Change subject: soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
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soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S

Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.

A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").

The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.

TGL also introduces parameters for customizing the default SVID:SSID.
These must be set or it will still use the FSP defaults.

Tested by checking lspci output on System76 darp7 (TGL-U).

References:
- b1fa231d76a ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S")
- TigerLake FSP Integration Guide
- Intel Document #631120-001

Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e
Signed-off-by: Tim Crawford 
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 55 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/56867/2