Change in coreboot[master]: soc/intel/alderlake: Implement PCH lock down configuration

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63692 )

Change subject: soc/intel/alderlake: Implement PCH lock down configuration
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Patch Set 4:

(1 comment)

File src/soc/intel/alderlake/lockdown.c:

https://review.coreboot.org/c/coreboot/+/63692/comment/9791754c_fcd608cc 
PS4, Line 41: if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
            : 		return;
            : 
            : 	/* Enable IOSF Primary Trunk Clock Gating */
            : 	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
> In CB:63640 the logic is inverted.To stay consistent it would look like:
>
> if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
>         pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
>
> But up to you.

yeah, I did that to avoid braces and indentation @Werner, do you think this is reasonable ? with CB:63640, the entire `pmc_lockdown_cfg` function we are not skipping when `USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM` is selected, hence had to use `invert` logic there