Change in coreboot[master]: cse_lite: Move global reset after MRC writeback

[Caveh Jalali (Code Review)]

Hello V Sowmya, Shelley Chen, Shaunak Saha, build bot (Jenkins), Jamie Ryu, Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44430

to look at the new patch set (#4).

Change subject: cse_lite: Move global reset after MRC writeback
......................................................................

cse_lite: Move global reset after MRC writeback

With CSE-lite enabled, we were going through the lengthy memory
training procedure twice on the first power-on boot or after full BIOS
SPI flash update. This moves the global reset performed to achieve the
CSE-lite RO to RW reboot to a later boot phase so that it happens
after the memory training data has been written to the MRC cache. Now,
the 2nd (and subsequent) reboot can utilize the memory training data
established during the 1st boot.

This reduces the first boot time by about 20s on a 16GB system.

Looking at the timing stats form cbmem, the normal boot penalty is
about 300ms - mostly attributed to running FspSiliconInit a 2nd
time. We will get this time back when the mrc_cache refactoring effort
lands (cb:44196, et. al).

BUG=b:162021048
TEST=Booted on volteer, confirmed 20s faster boot time.

Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235
Signed-off-by: Caveh Jalali 
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44430/4