[S] Change in coreboot[main]: soc/intel/common/gpio: add function to lock GPIO configuration

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Pranava Y N, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84901?usp=email )

Change subject: soc/intel/common/gpio: add function to lock GPIO configuration
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Patch Set 3:

(1 comment)

File src/soc/intel/common/block/gpio/gpio.c:

https://review.coreboot.org/c/coreboot/+/84901/comment/7dfa13dc_b3e03058?usp... :
PS3, Line 485: /* Clear lock for the exception PADs */
> we won't be able to clear the locking after we reaches ramstage (after FSP-S exits)

Yes. that is the intention. This function only updates the base table lock_action field. After the base table is overridden via fw_config for the final configuration in the mainboard.c, we perform configuration lock. Currently, this function is called to add the lock property to the table before we actually write to GPIO config registers prior to calling FSP-S. We could defer locking after FSP-S exit. The lock configuration bits are located in different registers other than the individual DW0/1 registers and we update those lock bits according to this GPIO base table.