Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75873?usp=email )
Change subject: intetool: Add support for 700 series PCH ......................................................................
intetool: Add support for 700 series PCH
The change does the following:
- adds PCH IDs for 700 series chipsets per the DOC# 619362 rev 2.2 - updates GPIO table for PCH-S per the DOC# 618659 rev 2.1
Change-Id: I4509ad714772ce90cdee5135227c02640acb6085 Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com --- M util/inteltool/gpio_groups.c M util/inteltool/gpio_names/alderlake_h.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h 4 files changed, 37 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/75873/1
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 752cb7d..953a60e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -222,11 +222,16 @@ case PCI_DEVICE_ID_INTEL_Q670: case PCI_DEVICE_ID_INTEL_Z690: case PCI_DEVICE_ID_INTEL_W680: - case PCI_DEVICE_ID_INTEL_W685: case PCI_DEVICE_ID_INTEL_WM690: case PCI_DEVICE_ID_INTEL_HM670: - case PCI_DEVICE_ID_INTEL_WM790: + case PCI_DEVICE_ID_INTEL_W790: + case PCI_DEVICE_ID_INTEL_Z790: + case PCI_DEVICE_ID_INTEL_H770: + case PCI_DEVICE_ID_INTEL_B760: case PCI_DEVICE_ID_INTEL_HM770: + case PCI_DEVICE_ID_INTEL_WM790: + case PCI_DEVICE_ID_INTEL_C262: + case PCI_DEVICE_ID_INTEL_C266: *community_count = ARRAY_SIZE(alderlake_pch_h_communities); *pad_stepping = 16; return alderlake_pch_h_communities; diff --git a/util/inteltool/gpio_names/alderlake_h.h b/util/inteltool/gpio_names/alderlake_h.h index 0a563f0..d3a9ed6 100644 --- a/util/inteltool/gpio_names/alderlake_h.h +++ b/util/inteltool/gpio_names/alderlake_h.h @@ -105,10 +105,10 @@ "GPP_D2", "SRCCLKREQ2#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D2", "GPP_D3", "SRCCLKREQ3#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D3", "GPP_D4", "SML1CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D4", - "GPP_D5", "n/a", "CNV_RF_RESET#", "n/a", "n/a", "n/a", "USB_C_GPP_D5", - "GPP_D6", "n/a", "n/a", "MODEM_CLKREQ", "n/a", "n/a", "USB_C_GPP_D6", - "GPP_D7", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D7", - "GPP_D8", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D8", + "GPP_D5", "I2S2_SFRM", "CNV_RF_RESET#", "n/a", "n/a", "n/a", "USB_C_GPP_D5", + "GPP_D6", "I2S2_TXD", "n/a", "MODEM_CLKREQ", "n/a", "n/a", "USB_C_GPP_D6", + "GPP_D7", "I2S2_RXD", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D7", + "GPP_D8", "I2S2_SCLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D8", "GPP_D9", "SML0CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D9", "GPP_D10", "SML0DATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D10", "GPP_D11", "SRCCLKREQ4#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D11", @@ -339,15 +339,15 @@ };
const char *const alderlake_pch_h_group_r_names[] = { - "GPP_R0", "HDA_BCLK", "n/a", "n/a", "HDACPU_BCLK", "n/a", "USB_C_GPP_R0", - "GPP_R1", "HDA_SYNC", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R1", - "GPP_R2", "HDA_SDO", "n/a", "n/a", "HDACPU_SDO", "n/a", "USB_C_GPP_R2", - "GPP_R3", "HDA_SDI0", "n/a", "n/a", "HDACPU_SDI", "n/a", "USB_C_GPP_R3", + "GPP_R0", "HDA_BCLK", "I2S0_SCLK", "n/a", "HDACPU_BCLK", "n/a", "USB_C_GPP_R0", + "GPP_R1", "HDA_SYNC", "I2S0_SFRM", "n/a", "n/a", "n/a", "USB_C_GPP_R1", + "GPP_R2", "HDA_SDO", "I2S0_TXD", "n/a", "HDACPU_SDO", "n/a", "USB_C_GPP_R2", + "GPP_R3", "HDA_SDI0", "I2S0_RXD", "n/a", "HDACPU_SDI", "n/a", "USB_C_GPP_R3", "GPP_R4", "HDA_RST#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R4", - "GPP_R5", "HDA_SDI1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R5", - "GPP_R6", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R6", - "GPP_R7", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R7", - "GPP_R8", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R8", + "GPP_R5", "HDA_SDI1", "I2S1_RXD", "n/a", "n/a", "n/a", "USB_C_GPP_R5", + "GPP_R6", "n/a", "I2S1_TXD", "n/a", "n/a", "n/a", "USB_C_GPP_R6", + "GPP_R7", "n/a", "I2S1_SFRM", "n/a", "n/a", "n/a", "USB_C_GPP_R7", + "GPP_R8", "n/a", "I2S1_SCLK", "n/a", "n/a", "n/a", "USB_C_GPP_R8", "GPP_R9", "DDSP_HPDA", "DISP_MISCA", "n/a", "n/a", "n/a", "USB_C_GPP_R9", "GPP_R10", "DDSP_HPDB", "DISP_MISCB", "n/a", "n/a", "n/a", "USB_C_GPP_R10", "GPP_R11", "DDSP_HPDC", "DISP_MISCC", "n/a", "n/a", "n/a", "USB_C_GPP_R11", diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 9d40148..97e64e2 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -402,11 +402,16 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q670, "Q670" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z690, "Z690" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W680, "W680" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W685, "W685" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM690, "WM690" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM670, "HM670" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM790, "WM790" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W790, "W790" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z790, "Z790" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H770, "H770" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B760, "B760" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM770, "HM770" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM790, "WM790" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C262, "C262" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C266, "C266" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL, "Elkhart Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JSL, "Jasper Lake" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 986a03c..02ee147 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -227,20 +227,26 @@ #define PCI_DEVICE_ID_INTEL_C256 0x438d #define PCI_DEVICE_ID_INTEL_W580 0x438f
-#define PCI_DEVICE_ID_INTEL_H610E 0x7a92 -#define PCI_DEVICE_ID_INTEL_Q670E 0x7a91 -#define PCI_DEVICE_ID_INTEL_R680E 0x7a90 #define PCI_DEVICE_ID_INTEL_H610 0x7a87 #define PCI_DEVICE_ID_INTEL_B660 0x7a86 #define PCI_DEVICE_ID_INTEL_H670 0x7a85 #define PCI_DEVICE_ID_INTEL_Q670 0x7a83 #define PCI_DEVICE_ID_INTEL_Z690 0x7a84 #define PCI_DEVICE_ID_INTEL_W680 0x7a88 -#define PCI_DEVICE_ID_INTEL_W685 0x7a8a #define PCI_DEVICE_ID_INTEL_WM690 0x7a8d #define PCI_DEVICE_ID_INTEL_HM670 0x7a8c -#define PCI_DEVICE_ID_INTEL_WM790 0x7a0d +#define PCI_DEVICE_ID_INTEL_R680E 0x7a90 +#define PCI_DEVICE_ID_INTEL_Q670E 0x7a91 +#define PCI_DEVICE_ID_INTEL_H610E 0x7a92 + +#define PCI_DEVICE_ID_INTEL_W790 0x7a8a +#define PCI_DEVICE_ID_INTEL_Z790 0x7a04 +#define PCI_DEVICE_ID_INTEL_H770 0x7a05 +#define PCI_DEVICE_ID_INTEL_B760 0x7a06 #define PCI_DEVICE_ID_INTEL_HM770 0x7a0c +#define PCI_DEVICE_ID_INTEL_WM790 0x7a0d +#define PCI_DEVICE_ID_INTEL_C262 0x7a14 +#define PCI_DEVICE_ID_INTEL_C266 0x7a13
#define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
-
Michał Żygowski (Code Review)