Change in coreboot[master]: soc/amd: Do SMM relocation via MSR

[Arthur Heymans (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held.
Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/64872

to look at the new patch set (#7).

Change subject: soc/amd: Do SMM relocation via MSR
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soc/amd: Do SMM relocation via MSR

AMD CPUs have a convenient MSR that allows to set the SMBASE in the save
state without ever entering SMM (e.g. at the default 0x30000 address).
This has been a feature in all AMD CPUs since at least AMD K8. This
allows to do relocation in parallel in ramstage and without setting up a
relocation handler, which likely results in a speedup. The more cores
the higher the speedup as relocation was happening sequentially. On a 4
core AMD picasso system this results in 33ms boot speedup.

TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM
is correctly relocated with the BSP correctly entering the smihandler.

Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b
Signed-off-by: Arthur Heymans 
---
M src/cpu/amd/smm/smm_helper.c
M src/cpu/x86/Kconfig
M src/cpu/x86/mp_init.c
M src/soc/amd/common/Kconfig.common
4 files changed, 27 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/64872/7