[S] Change in coreboot[main]: soc/intel/snowridge: add CPU and PCIe definitions for SNR - coreboot-gerrit

4 Jul 2024


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Shuo Liu has posted comments on this change by yuchi.chen@intel.com. ( https://review.coreboot.org/c/coreboot/+/83314?usp=email )
Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83314/comment/a8c58869_a081f7f2?usp... :
PS2, Line 8:
...
Add CPU and PCIe definitions for SNR
oops, please follow Felix's comment, but capitalize the 1st letter (add -> Add)
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Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Gerrit-Change-Number: 83314
Gerrit-PatchSet: 2
Gerrit-Owner: yuchi.chen@intel.com
Gerrit-Reviewer: Jérémy Compostella jeremy.compostella@intel.com
Gerrit-Reviewer: Shuo Liu shuo.liu@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Felix Singer service+coreboot-gerrit@felixsinger.de
Gerrit-Attention: yuchi.chen@intel.com
Gerrit-Comment-Date: Thu, 04 Jul 2024 01:53:58 +0000
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Comment-In-Reply-To: Shuo Liu shuo.liu@intel.com