Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Ravi Kumar Bokka, Shelley Chen, Hung-Te Lin, Nico Huber, Paul Menzel, Rex-BC Chen, Julius Werner, Arthur Heymans, Jianjun Wang.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot_tables: Add PCIe info to coreboot table
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Patch Set 19:

(1 comment)

Patchset:

PS9:
> > As far as I'm aware this is their current draft patch: CB:57615. […]

Ravi, could you answer the following questions?

1. Does qualcomm's pcie implementation has the concept of "controller base address"? Does it make sense to set ctrl_base = 0x40000000, atu_base = ctrl_base + 0x1000, mmio_base = ctrl_base + 0x100000?
2. Are atu_base and mmio_base expected to be different for each qualcomm SoC? What about the offsets 0x1000 and 0x100000?
3. Where does the MMIO_LENGTH value (0x100000 = 1MB) come from? Is it likely to be changed for future qualcomm SoCs? Can this value be calculated somehow (for example, by 4KB * devices_per_bus * funcs_per_device = 4KB * 32 * 8)?