Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76020?usp=email )
Change subject: mb/{cfl,cml,whl}: Use true/false macros for eist_enable dt option ......................................................................
mb/{cfl,cml,whl}: Use true/false macros for eist_enable dt option
The true/false macros give the reader a better understanding about how the option should be used. Thus, replace 0/1 with false/true.
While on it, remove the quotes from the option name and from the value.
Coffeelake, Cometlake and Whiskeylake mainboards which use that option were changed by the following command ran from the top level directory.
dt_line="chip soc/intel/cannonlake" && \ option="eist_enable" && \ grep -r "${dt_line}" src/mainboard | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/"${option}".*=.*"1"/${option} = true/g" -e "s/"${option}".*=.*"0"/${option} = false/g"
Change-Id: I9428b3f59bb776cd51090b1354684a2d5dc08b82 Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/purism/librem_cnl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb 12 files changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/76020/1
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 6e11a5a..24e5834 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -17,7 +17,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index dd585cc..cdf22a8 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -108,7 +108,7 @@ register s0ix_enable = false
# Enable Turbo - register "eist_enable" = "1" + register eist_enable = true
register "common_soc_config" = "{ .gspi[0] = { diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index f448a20..650854c 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
register "cpu_pl2_4_cfg" = "baseline"
diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb index 944f069..ab58893 100644 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index ef544cd..7f1ff33 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# Graphics # IGD Displays diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 8bd9d60..ed47b74 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -16,7 +16,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index 1e0ff8d..f609b2f 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -16,7 +16,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index a35dfea..8982031 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -16,7 +16,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index f46b289..1dc3623 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -16,7 +16,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index c794d06..e3cc3dc 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -16,7 +16,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index a2d56d7..ef876ca 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -16,7 +16,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index ce0f376..c7369b4 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -16,7 +16,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled"