[XS] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Modify GPP_C1 setting

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83818?usp=email )

Change subject: mb/google/nissa/var/pujjoga: Modify GPP_C1 setting
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mb/google/nissa/var/pujjoga: Modify GPP_C1 setting

Confirm with EE, the GPP_C1 don't need PU 20K.
So modify GPP_C1 setting to remove PU 20k

Schematic version: 500E_GEN4S_ADL_N_MB_0418

BUG=b:358162951
TEST=Build and boot on pujjoga.

Change-Id: I7ad16cd29ab467d3eac74dab40522c577d91c747
Signed-off-by: Leo Chou 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83818
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
Reviewed-by: Derek Huang 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/brya/variants/pujjoga/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Eric Lai: Looks good to me, approved
  build bot (Jenkins): Verified
  Derek Huang: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/pujjoga/gpio.c b/src/mainboard/google/brya/variants/pujjoga/gpio.c
index 2950605..1390e08 100644
--- a/src/mainboard/google/brya/variants/pujjoga/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjoga/gpio.c
@@ -17,7 +17,7 @@
    /* B6  : SOC_I2C_SUB_SCL */
    PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
    /* C1  : SMBDATA ==> USI_RST_L */
-	PAD_CFG_TERM_GPO(GPP_C1, 1, UP_20K, DEEP),
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
    /* D3  : test point */
    PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
    /* D6  : SRCCLKREQ1# ==> WWAN_EN */