HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15439
-gerrit
commit 3af91f1a1a639665ae5f05ab680e7d3ba2e68f64 Author: Elyes HAOUAS ehaouas@noos.fr Date: Sun Jun 26 17:46:21 2016 +0200
SPD: Add CAS latency 2
CAS latency = 2 support added for DDR2.
Change-Id: I08d72a61c27ff0eab19e500a2f547a5e946de2f0 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/include/spd.h | 1 + src/northbridge/intel/i945/raminit.c | 17 +++++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/include/spd.h b/src/include/spd.h index 6424d33..0bc7898 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -147,6 +147,7 @@ enum spd_memory_type { #define SPD_CAS_LATENCY_3_5 0x20 #define SPD_CAS_LATENCY_4_0 0x40
+#define SPD_CAS_LATENCY_DDR2_2 (1 << 2) #define SPD_CAS_LATENCY_DDR2_3 (1 << 3) #define SPD_CAS_LATENCY_DDR2_4 (1 << 4) #define SPD_CAS_LATENCY_DDR2_5 (1 << 5) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 59a31de..dc41e53 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -459,7 +459,8 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) u8 cas_mask;
/* Setup CAS mask with all supported CAS Latencies */ - cas_mask = SPD_CAS_LATENCY_DDR2_3 | + cas_mask = SPD_CAS_LATENCY_DDR2_2 | + SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4 | SPD_CAS_LATENCY_DDR2_5;
@@ -506,7 +507,9 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 sysinfo->memory_frequency = 0; sysinfo->cas = 0;
- if (cas_mask & SPD_CAS_LATENCY_DDR2_3) { + if (cas_mask & SPD_CAS_LATENCY_DDR2_2) { + lowest_common_cas = 2; + } else if (cas_mask & SPD_CAS_LATENCY_DDR2_3) { lowest_common_cas = 3; } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) { lowest_common_cas = 4; @@ -539,10 +542,14 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 highest_supported_cas = 4; } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { highest_supported_cas = 3; + } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_2) { + highest_supported_cas = 2; } else { die("Invalid max. CAS.\n"); } - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { + if (current_cas_mask & SPD_CAS_LATENCY_DDR2_2) { + current_cas = 2; + } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { current_cas = 3; } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { current_cas = 4; @@ -581,7 +588,9 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 case 1: sysinfo->memory_frequency = 533; break; case 2: sysinfo->memory_frequency = 667; break; } - if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) { + if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_2) { + sysinfo->cas = 2; + } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) { sysinfo->cas = 3; } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) { sysinfo->cas = 4;
-
HAOUAS Elyes