[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable GSPI interface

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72706 )

Change subject: mb/intel/mtlrvp: Enable GSPI interface
......................................................................

mb/intel/mtlrvp: Enable GSPI interface

This patch enables GSPI [1] interface for mtlrvp based on mtlrvp
schematics.

BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump and
able to boot mtlrvp (LP5/DDR5) to ChromeOS. (Base patch for CB:71223)
SPI[0].Mode                 = 0
SPI[0].DefaultCsOutput      = 0
SPI[0].CsMode               = 0
SPI[0].CsState              = 0
SPI[1].Mode                 = 1
SPI[1].DefaultCsOutput      = 0
SPI[1].CsMode               = 0
SPI[1].CsState              = 0

Signed-off-by: Harsha B R 
Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860
Signed-off-by: Jamie Ryu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72706
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Sridhar Siricilla 
---
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
1 file changed, 47 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Sridhar Siricilla: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 53464f9..ddb80026 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -69,6 +69,21 @@
    	},
    }"

+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_cs_mode" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+	}"
+
+	register "serial_io_gspi_cs_state" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+	}"
+
    device domain 0 on
    	device ref igpu on end
    	device ref heci1 on end
@@ -129,6 +144,7 @@
    	device ref i2c5 on end
    	device ref shared_sram on end
    	device ref uart0 on end
+		device ref gspi1 on end
    	device ref smbus on end
    end
 end