Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36757 )
Change subject: mb/*/*(ich7/x4x): Use common early southbridge init ......................................................................
mb/*/*(ich7/x4x): Use common early southbridge init
One functional change is that southbridge GPIO init is moved after console init.
Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/northbridge/intel/x4x/early_init.c 7 files changed, 8 insertions(+), 104 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36757/1
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 7d35204..404b074 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -21,7 +21,6 @@ #include <arch/romstage.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/nuvoton/common/nuvoton.h> @@ -36,12 +35,6 @@
static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); @@ -59,12 +52,6 @@ /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - - ich7_setup_cir(); }
void mainboard_romstage_entry(void) @@ -82,6 +69,7 @@
enable_smbus();
+ i82801gx_early_setup(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 009c3cf..6d804dd 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/msr.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> @@ -129,21 +128,6 @@ return need_reset; }
-static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -153,13 +137,13 @@
/* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
+ i82801gx_early_setup(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index e138445..ac17bf9 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/ite/common/ite.h> @@ -33,12 +32,6 @@
static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); ite_reg_write(GPIO_DEV, 0x26, 0x04); @@ -62,13 +55,7 @@ RCBA16(D30IR) = 0x3241; RCBA16(D29IR) = 0x0237;
- /* Enable IOAPIC. */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - RCBA32(FD) |= FD_INTLAN; - - ich7_setup_cir(); }
void mainboard_romstage_entry(void) @@ -93,6 +80,7 @@
enable_smbus();
+ i82801gx_early_setup(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 01e959d..6664993 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> @@ -36,19 +35,12 @@ * We should use standard gpio.h eventually */
-static void mb_gpio_init(void) +static void mb_lpc_init(void) { pci_devfn_t dev;
/* Southbridge GPIOs. */ dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); @@ -91,12 +83,6 @@ RCBA32(D31IR) = 0x00410032; RCBA32(D29IR) = 0x32100237; RCBA32(D27IR) = 0x00000000; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - - ich7_setup_cir(); }
void mainboard_romstage_entry(void) @@ -108,7 +94,7 @@
/* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_gpio_init(); + mb_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Disable SIO reboot */ @@ -118,6 +104,7 @@
enable_smbus();
+ i82801gx_early_setup(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 1033048..9c80c2c 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -21,7 +21,6 @@ #include <arch/romstage.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> @@ -32,12 +31,6 @@
static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); pnp_set_logical_device(SERIAL_DEV); @@ -49,12 +42,6 @@ /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); }
void mainboard_romstage_entry(void) @@ -73,6 +60,7 @@
enable_smbus();
+ i82801gx_early_setup(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 9f304d5..91ac6c8 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -17,7 +17,6 @@
#include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> @@ -28,21 +27,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0)
-static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -52,13 +36,13 @@
/* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
+ i82801gx_early_setup(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d48b8f0..f89411e 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -41,12 +41,6 @@ /* Setup EPBAR. */ pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
- /* Setup PMBASE */ - if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); - } - /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR);
@@ -59,15 +53,6 @@ pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
- if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */ - outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */ - outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */ - printk(BIOS_DEBUG, " done.\n"); - } - if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36757
to look at the new patch set (#3).
Change subject: mb/*/*(ich7/x4x): Use common early southbridge init ......................................................................
mb/*/*(ich7/x4x): Use common early southbridge init
One functional change is that southbridge GPIO init is moved after console init.
Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/northbridge/intel/x4x/early_init.c 7 files changed, 8 insertions(+), 104 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36757/3
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36757
to look at the new patch set (#4).
Change subject: mb/*/*(ich7/x4x): Use common early southbridge init ......................................................................
mb/*/*(ich7/x4x): Use common early southbridge init
One functional change is that southbridge GPIO init is moved after console init.
Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/northbridge/intel/x4x/early_init.c 7 files changed, 8 insertions(+), 104 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36757/4
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36757 )
Change subject: mb/*/*(ich7/x4x): Use common early southbridge init ......................................................................
Patch Set 4: Code-Review+1
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36757 )
Change subject: mb/*/*(ich7/x4x): Use common early southbridge init ......................................................................
Patch Set 6: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36757 )
Change subject: mb/*/*(ich7/x4x): Use common early southbridge init ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36757 )
Change subject: mb/*/*(ich7/x4x): Use common early southbridge init ......................................................................
mb/*/*(ich7/x4x): Use common early southbridge init
One functional change is that southbridge GPIO init is moved after console init.
Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/northbridge/intel/x4x/early_init.c 7 files changed, 8 insertions(+), 104 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 9de168c..b054897 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/romstage.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/nuvoton/common/nuvoton.h> @@ -35,12 +34,6 @@
static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); @@ -58,12 +51,6 @@ /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - - ich7_setup_cir(); }
void mainboard_romstage_entry(void) @@ -81,6 +68,7 @@
enable_smbus();
+ i82801gx_early_init(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 4653b42..de3972d 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -23,7 +23,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/msr.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> @@ -128,21 +127,6 @@ return need_reset; }
-static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -152,13 +136,13 @@
/* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
+ i82801gx_early_init(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index f423c11..45ff7e4 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -20,7 +20,6 @@ #include <arch/romstage.h> #include <device/pci_ops.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/ite/common/ite.h> @@ -32,12 +31,6 @@
static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); ite_reg_write(GPIO_DEV, 0x26, 0x04); @@ -61,13 +54,7 @@ RCBA16(D30IR) = 0x3241; RCBA16(D29IR) = 0x0237;
- /* Enable IOAPIC. */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - RCBA32(FD) |= FD_INTLAN; - - ich7_setup_cir(); }
void mainboard_romstage_entry(void) @@ -92,6 +79,7 @@
enable_smbus();
+ i82801gx_early_init(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index fa69d12..16b157b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> @@ -35,19 +34,12 @@ * We should use standard gpio.h eventually */
-static void mb_gpio_init(void) +static void mb_lpc_init(void) { pci_devfn_t dev;
/* Southbridge GPIOs. */ dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); @@ -90,12 +82,6 @@ RCBA32(D31IR) = 0x00410032; RCBA32(D29IR) = 0x32100237; RCBA32(D27IR) = 0x00000000; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - - ich7_setup_cir(); }
void mainboard_romstage_entry(void) @@ -107,7 +93,7 @@
/* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_gpio_init(); + mb_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Disable SIO reboot */ @@ -117,6 +103,7 @@
enable_smbus();
+ i82801gx_early_init(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index c0127b6..0d7c162 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/romstage.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> @@ -31,12 +30,6 @@
static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); pnp_set_logical_device(SERIAL_DEV); @@ -48,12 +41,6 @@ /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); }
void mainboard_romstage_entry(void) @@ -72,6 +59,7 @@
enable_smbus();
+ i82801gx_early_init(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index d632d9d..8be2c86 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -17,7 +17,6 @@
#include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> @@ -27,21 +26,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0)
-static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -51,13 +35,13 @@
/* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
+ i82801gx_early_init(); x4x_early_init();
s3_resume = southbridge_detect_s3_resume(); diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d48b8f0..f89411e 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -41,12 +41,6 @@ /* Setup EPBAR. */ pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
- /* Setup PMBASE */ - if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); - } - /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR);
@@ -59,15 +53,6 @@ pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
- if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */ - outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */ - outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */ - printk(BIOS_DEBUG, " done.\n"); - } - if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
-
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