Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42716 )
Change subject: soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define ......................................................................
soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define
Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
BUG=b:159187889 BRANCH=none TEST=none
Change-Id: Ie63e4f1fcdea130f8faed5c0d34a6a96759946b6 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/soc/intel/cannonlake/include/soc/usb.h 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42716/1
diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 247b0ba..ac5776c 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -136,4 +136,11 @@ .tx_downscale_amp = 0x00, \ }
+/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1)) + #endif
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42716 )
Change subject: soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define ......................................................................
Patch Set 2: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42716 )
Change subject: soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define ......................................................................
soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define
Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
BUG=b:159187889 BRANCH=none TEST=none
Change-Id: Ie63e4f1fcdea130f8faed5c0d34a6a96759946b6 Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42716 Reviewed-by: Sam McNally sammc@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/include/soc/usb.h 1 file changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 247b0ba..ac5776c 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -136,4 +136,11 @@ .tx_downscale_amp = 0x00, \ }
+/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1)) + #endif