[XS] Change in coreboot[main]: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64 - coreboot-gerrit

27 Aug 2024


      Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Tarun.
Subrata Banik has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84085?usp=email )
Change subject: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64
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Patch Set 2: Code-Review+2
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Gerrit-Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545
Gerrit-Change-Number: 84085
Gerrit-PatchSet: 2
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