[S] Change in coreboot[master]: drivers/intel/fsp2_0: Introduce early MRC cache store

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nico Huber, Paul Menzel, Raul Rangel.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77556?usp=email )

Change subject: drivers/intel/fsp2_0: Introduce early MRC cache store
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Patch Set 4:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/77556/comment/0415bd48_1ed782c2 :
PS3, Line 43: +--------------------+--------------------------+--------------------------+-------------------------+
> Not sure if the long tables are necessary as only a single item changes.

This CL is meant to change the order in while the MRC cache being handled and will get handled, hence, its better to capture the change in details.

The thing that is problematic is the gerrit review is unable to handle the long length ascii rows which shouldn't be a problem in git log

https://review.coreboot.org/c/coreboot/+/77556/comment/c7c626d5_28fd9c74 :
PS3, Line 47:
> Maybe mention that this effectively undoes commit 7b5a93153a17, and why,
> i.e. what changed since then (CSE sync, CBMEM caching).

done