[XS] Change in coreboot[main]: mb/google/brya/var/orisa: Remove redundant defaults from overridetree

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83674?usp=email )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/brya/var/orisa: Remove redundant defaults from overridetree
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mb/google/brya/var/orisa: Remove redundant defaults from overridetree

Streamline variant-level overrides by removing redundant entries that
already exist in either the SoC-level or the platform-level configurations.

BUG=None
TEST=emerge-nissa coreboot

Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e
Signed-off-by: Rishika Raj 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674
Tested-by: build bot (Jenkins) 
Reviewed-by: Dinesh Gehlot 
Reviewed-by: Subrata Banik 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/brya/variants/orisa/overridetree.cb
1 file changed, 0 insertions(+), 4 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  Eric Lai: Looks good to me, approved
  build bot (Jenkins): Verified
  Dinesh Gehlot: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index 543a667..92909ab 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -86,10 +86,7 @@
    register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"     # USB2_A0
    register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"     # USB2_A1
    register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 Camera
-	register "usb2_ports[3]" = "USB2_PORT_EMPTY"            # Disable USB2 Port 4
    register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB2_C0
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"            # Disable USB2 Port 7
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"            # Disable USB2 Port 8

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A0
    register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A1
@@ -511,7 +508,6 @@
    		end
    	end #I2C5
    	device ref heci1 on end
-		device ref pcie_rp7 off end
    	device ref emmc on
    		probe STORAGE STORAGE_UNKNOWN
    		probe STORAGE STORAGE_EMMC