Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Adjust timB to prevent overflow

the following patch was just integrated into master:
commit d912f1d4f973f415a431932b71e9cee0b1c82549
Author: Patrick Rudolph 
Date:   Mon Feb 15 20:07:42 2016 +0100

nb/intel/sandybridge/raminit: Adjust timB to prevent overflow

Improved version of
    I1a115a45d5febf351d89721ece79eaf43f7ee8a0

The first version wasn't well tested due to the lack of hardware
    and it was to aggressive.

With timC being direct function of timB's 6 LSBs it's critical to match
    timC and timB.
    Some tests increments the value of timB by a small value,
    which might cause the 6bit value to overflow, if it's close
    to 0x3F.
    Increment the value by a small offset if it's likely
    to overflow, to make sure it won't overflow while running
    tests and bricks the system due to a non matching timC.

In comparission to the first attempt, only 4 out of 128 timB values
    are considered bad.

Needs test on real hardware !

Fixes a "edge write discovery failed" on my test system.

Test system:
     * Intel IvyBridge
     * Gigabyte GA-B75M-D3H

Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d
    Signed-off-by: Patrick Rudolph 
    Reviewed-on: https://review.coreboot.org/13714
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer

See https://review.coreboot.org/13714 for details.

-gerrit