Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Saurabh Mishra.
Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 22:
(3 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/060d2b40_89eda6bc?usp... :
PS12, Line 204: default 12
Acknowledged
10 RPs for PTL-H (45W) and 12 RPs for PTL-UH as per EDS 815002
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/cbef81d5_c6c36ca9?usp... :
PS22, Line 243: TODO
give one space after `#`
File src/soc/intel/pantherlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/9f76b171_05514e5e?usp... :
PS22, Line 11: 2
should be 4 and guard based on the PCH Kconfig.
if you are not keep on adding PTL-H (45W) support then keeping 4 alone will work for now.
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