[S] Change in coreboot[master]: mb/google/myst: Update PCIe romstage gpios

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jon Murphy, Martin Roth, Tim Van Patten.

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75699?usp=email )

Change subject: mb/google/myst: Update PCIe romstage gpios
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Patch Set 2:

(1 comment)

File src/mainboard/google/myst/variants/baseboard/gpio.c:

https://review.coreboot.org/c/coreboot/+/75699/comment/cf26f805_17ca968b :
PS2, Line 207: CLK_REQ3_L
> The SSD clock request line is required before PCIe link training. […]

I think we did not do it in Skyrim since all the concerned GPIOs, at least the AUX_RST_L GPIOs, were in S0 domain. On Myst, all the AUX_RST_L GPIOs are in S5 domain. Since we are hearing different things about warm reset, I will recommend to initialize AUX_RST_L and CLK_REQ_L lines for all WLAN, SD and SSD PCIe GPP ports before PCIe link training. If you want to do that as a follow-up CL, I am fine. But strongly recommend to do that in preparation for warm reset. Otherwise when warm reset is enabled in SoC code, we may be observing failures/regressions.