Change in coreboot[master]: soc/intel: transition full control over PM Timer from FSP to coreboot

[Michael Niewöhner (Code Review)]

Attention is currently required from: Lance Zhao,  Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph.
Hello  Felix Singer, Lance Zhao, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/57933

to look at the new patch set (#27).

Change subject: soc/intel: transition full control over PM Timer from FSP to coreboot
......................................................................

soc/intel: transition full control over PM Timer from FSP to coreboot

Set `EnableTcoTimer=1` in order to keep FSP from
 1) enabling ACPI Timer emulation in uCode.
 2) disabling the PM ACPI Timer.

Both actions are now done in coreboot.

`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.

Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/elkhartlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/jasperlake/fsp_params.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/tigerlake/fsp_params.c
7 files changed, 66 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57933/27