Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72659 )
Change subject: soc/amd: Use common reset code for CZN & MDN SoCs ......................................................................
soc/amd: Use common reset code for CZN & MDN SoCs
This switches the Cezanne & Mendocino SoCs to use the common reset code. This patch does not change any behavior on those chips.
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/fch.c D src/soc/amd/cezanne/reset.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/mendocino/fch.c D src/soc/amd/mendocino/reset.c 8 files changed, 22 insertions(+), 76 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 35c2927..e1ab7b8 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -55,6 +55,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5313e0d..a8474e2 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -12,18 +12,15 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c
verstage-y += i2c.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c
romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c
@@ -37,7 +34,6 @@ ramstage-y += graphics.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 0936c5e..f065c8e 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/gpio.h> #include <amdblocks/i2c.h> #include <amdblocks/smi.h> @@ -130,11 +131,6 @@ PM_ACPI_TIMER_EN_EN); }
-static void fch_init_resets(void) -{ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); -} - /* Configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -204,7 +200,7 @@
void fch_init(void *chip_info) { - fch_init_resets(); + set_resets_to_cold(); i2c_soc_init(); fch_init_acpi_ports();
diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c deleted file mode 100644 index 1360bd5..0000000 --- a/src/soc/amd/cezanne/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Warm resets are not supported and must be executed as cold */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 7faa479..5b274f9 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 7d7033a..1dc0773 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -14,19 +14,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c
verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c
romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c
@@ -39,7 +36,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index abe2dc1..5edbcc6 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -5,6 +5,7 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -126,11 +127,6 @@ PM_ACPI_TIMER_EN_EN); }
-static void fch_init_resets(void) -{ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); -} - /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -202,7 +198,7 @@
void fch_init(void *chip_info) { - fch_init_resets(); + set_resets_to_cold(); i2c_soc_init(); fch_init_acpi_ports();
diff --git a/src/soc/amd/mendocino/reset.c b/src/soc/amd/mendocino/reset.c deleted file mode 100644 index ac0c981..0000000 --- a/src/soc/amd/mendocino/reset.c +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Warm resets are not supported and must be executed as cold */ - do_cold_reset(); -} - -void do_board_reset(void) -{ - do_cold_reset(); -}
-
Felix Held (Code Review)